Parity is also checked when a UTLB entry is read using the TLBHI and TLBLO registers. When
a parity error is detected in this case, the entry is marked invalid by clearing the valid bit.
Enabling fault tolerance does not increase the MMU block RAM size, since a spare bit is
available for the parity.
Branch Target Cache Protection
To protect block RAM in the Branch Target Cache, parity is used. When a parity error is
detected when looking up a branch target address, the address is ignored, forcing a normal
branch.
When a new branch address is written to the Branch Target Cache, parity is calculated. One
parity bit is used for each address.
Enabling fault tolerance does not increase the Branch Target Cache block RAM size, since a
spare bit is available for the parity.
Exception Handling
With fault tolerance enabled, if an error occurs in LMB block RAM, the LMB BRAM Interface
Controller generates error signals on the LMB interface.
If exceptions are enabled in MicroBlaze, by setting the EE bit in the Machine Status Register,
the uncorrectable error signal either generates an instruction bus exception or a data bus
exception, depending on the affected interface.
Should a bus exception occur when an exception is in progress, MicroBlaze is halted, and
the external error signal
execute an instruction corrupted by an uncorrectable error.
Software Support
Scrubbing
To ensure that bit errors are not accumulated in block RAMs, they must be periodically
scrubbed.
The standalone BSP provides the function
entire LMB block RAM and all MicroBlaze internal block RAMs used in a particular
configuration. This function is intended to be called periodically from a timer interrupt
routine.
The following example code illustrates how this can be done.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
is set. This behavior ensures that it is impossible to
MB_Error
microblaze_scrub()
www.xilinx.com
Chapter 2: MicroBlaze Architecture
to perform scrubbing of the
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