Xilinx MicroBlaze Reference Manual page 136

Table 3-4: AXI Memory Mapped Interface Parameters (Cont'd)
Interface
M_AXI_DC C_M_AXI_DC_DATA_WIDTH
M_ACE_DC
M_AXI_IC NUM_READ_OUTSTANDING
M_ACE_IC
M_AXI_DC NUM_READ_OUTSTANDING
M_ACE_DC
M_AXI_DC NUM_WRITE_OUTSTANDING
M_ACE_DC
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Chapter 3: MicroBlaze Signal Interface Description
Parameter
32: Default, single word accesses and burst accesses
with C_DCACHE_LINE_LEN word busts used with AXI4
and ACE.
Write bursts are only used with AXI4 when
C_DCACHE_USE_WRITEBACK is set to 1.
128: Used when C_DCACHE_DATA_WIDTH is set to 1
and C_DCACHE_LINE_LEN is set to 4 with AXI4. Only
single accesses can occur.
256: Used when C_DCACHE_DATA_WIDTH is set to 1
and C_DCACHE_LINE_LEN is set to 8 with AXI4. Only
single accesses can occur.
512: Used when C_DCACHE_DATA_WIDTH is set to 2, or
when it is set to 1 and C_DCACHE_LINE_LEN is set to
16 with AXI4. Only single accesses can occur.
1: Default for 128-bit, 256-bit and 512-bit masters, a
single outstanding read.
2: Default for 32-bit masters, 2 simultaneous
outstanding reads.
8: Used for 32-bit masters when C_ICACHE_STREAMS is
set to 1, allowing 8 simultaneous outstanding reads.
Can be set to 1, 2, or 8.
1: Default for 128-bit, 256-bit and 512-bit masters, a
single outstanding read.
2: Default for 32-bit masters, 2 simultaneous
outstanding reads.
Can be set to 1 or 2.
32: Default, 32 simultaneous outstanding writes.
Can be set to 1, 2, 4, 8, 16, or 32.
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