Xilinx MicroBlaze Reference Manual page 20

is performed based on the existence of the reservation established by the preceding LWX
instruction. If the reservation exists when the store is executed, the store is performed and
MSR[C] is cleared to 0. If the reservation does not exist when the store is executed, the
target memory location is not modified and MSR[C] is set to 1.
If the store is successful, the sequence of instructions from the semaphore load to the
semaphore store appear to be executed atomically—no other device modified the
semaphore location between the read and the update. Other devices can read from the
semaphore location during the operation. For a semaphore operation to work properly, the
LWX instruction must be paired with an SWX instruction, and both must specify identical
addresses. The reservation granularity in MicroBlaze is a word. For both instructions, the
address must be word aligned. No unaligned exceptions are generated for these
instructions.
The conditional store is always attempted when a reservation exists, even if the store
address does not match the load address that set the reservation.
Only one reservation can be maintained at a time. The address associated with the
reservation can be changed by executing a subsequent LWX instruction. The conditional
store is performed based upon the reservation established by the last LWX instruction
executed. Executing an SWX instruction always clears a reservation held by the processor,
whether the address matches that established by the LWX or not.
Reset, interrupts, exceptions, and breaks (including the BRK and BRKI instructions) all clear
the reservation.
The following provides general guidelines for using the LWX and SWX instructions:
• The LWX and SWX instructions should be paired and use the same address.
• An unpaired SWX instruction to an arbitrary address can be used to clear any
reservation held by the processor.
• A conditional sequence begins with an LWX instruction. It can be followed by memory
accesses and/or computations on the loaded value. The sequence ends with an SWX
instruction. In most cases, failure of the SWX instruction should cause a branch back to
the LWX for a repeated attempt.
• An LWX instruction can be left unpaired when executing certain synchronization
primitives if the value loaded by the LWX is not zero. An implementation of Test and Set
exemplifies this:
loop: lwx
bnei
addik r5,r5,1
swx
addic r5,r0,0
bnei
next:
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
r5,r3,r0 ; load and reserve
r5,next ; branch if not equal to zero
; increment value
r5,r3,r0 ; try to store non-zero value
; check reservation
r5,loop ; loop if reservation lost
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Chapter 2: MicroBlaze Architecture
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