Xilinx MicroBlaze Reference Manual page 147

Read and Write Data Steering
The MicroBlaze data-side bus interface performs the read steering and write steering
required to support the following transfers:
• byte, halfword, and word transfers to word devices
• byte and halfword transfers to halfword devices
• byte transfers to byte devices
MicroBlaze does not support transfers that are larger than the addressed device. These
types of transfers require dynamic bus sizing and conversion cycles that are not supported
by the MicroBlaze bus interface. Data steering for read cycles are shown in
Table 3-9, and data steering for write cycles are shown in
Big endian format is only available when using the MMU in virtual or protected mode
( > 1) or when reorder instructions are enabled (
C_USE_MMU
Table 3-8: Big Endian Read Data Steering (Load to Register rD)
Address
[30:31]
11
10
01
00
10
00
00
Table 3-9: Little Endian Read Data Steering (Load to Register rD)
Address
[30:31]
11
10
01
00
10
00
00
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Byte_Enable
Transfer Size
[0:3]
0001 byte
0010 byte
0100 byte
1000 byte
0011 halfword
1100 halfword
1111 word
Byte_Enable
Transfer Size
[0:3]
1000 byte
0100 byte
0010 byte
0001 byte
1100 halfword
0011 halfword
1111 word
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Chapter 3: MicroBlaze Signal Interface Description
Table 3-10
C_USE_REORDER_INSTR
Register rD Data
rD[0:7] rD[8:15] rD[16:23] rD[24:31]
Byte0 Byte1
Register rD Data
rD[0:7] rD[8:15] rD[16:23] rD[24:31]
Byte0 Byte1
Table 3-8 and
and Table 3-11.
= 1).
Byte3
Byte2
Byte1
Byte0
Byte2 Byte3
Byte0 Byte1
Byte2 Byte3
Byte0
Byte1
Byte2
Byte3
Byte0 Byte1
Byte2 Byte3
Byte2 Byte3
147
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