Xilinx MicroBlaze Reference Manual page 28

Table 2-11: Exception Status Register (ESR)
Bits Name
0:18 Reserved
19 DS
20:26 ESS
27:31 EC
Table 2-12: Exception Specific Status (ESS)
Exception
Cause
Unaligned 20
Data Access
21
22:26
Illegal 20:26
Instruction
Instruction 20
bus error
21:26
Data bus 20
error
21:26
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Delay Slot Exception.
0 = not caused by delay slot instruction
1 = caused by delay slot instruction
Read-only
Exception Specific Status
For details refer to
Read-only
Exception Cause
00000 = Stream exception
00001 = Unaligned data access exception
00010 = Illegal op-code exception
00011 = Instruction bus error exception
00100 = Data bus error exception
00101 = Divide exception
00110 = Floating point unit exception
00111 = Privileged instruction exception
00111 = Stack protection violation exception
10000 = Data storage exception
10001 = Instruction storage exception
10010 = Data TLB miss exception
10011 = Instruction TLB miss exception
Read-only
Bits Name
W Word Access Exception
0 = unaligned halfword access
1 = unaligned word access
S Store Access Exception
0 = unaligned load access
1 = unaligned store access
Rx Source/Destination Register
General purpose register used as source (Store) or
destination (Load) in unaligned access
Reserved
ECC Exception caused by ILMB correctable or
uncorrectable error
Reserved
ECC Exception caused by DLMB correctable or
uncorrectable error
Reserved
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Chapter 2: MicroBlaze Architecture
Description
Table 2-12.
Description
Reset Value
0
See Table 2-12
0
Reset Value
0
0
0
0
0
0
0
0
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