Xilinx MicroBlaze Reference Manual page 29

Table 2-12: Exception Specific Status (ESS) (Cont'd)
Exception
Cause
Divide 20
21:26
Floating 20:26
point unit
Privileged 20:26
instruction
Stack 20:26
protection
violation
Stream 20:22
23:26
Data 20
storage
21
22:26
Instruction 20
storage
21:26
Data TLB 20
miss
21
22:26
Instruction 20:26
TLB miss
Branch Target Register (BTR)
The Branch Target Register only exists if the MicroBlaze processor is configured to use
exceptions. The register stores the branch target address for all delay slot branch
instructions executed while MSR[EIP] = 0. If an exception is caused by an instruction in a
delay slot (that is, ESR[DS]=1), the exception handler should return execution to the address
stored in BTR instead of the normal exception return address stored in R17. When read with
the MFS instruction, the BTR is specified by setting Sa = 0x000B. The BTR register is
illustrated in Figure 2-7
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Bits Name
DEC Divide - Division exception cause
0 = Divide-By-Zero
1 = Division Overflow
Reserved
Reserved
Reserved
Reserved
Reserved
FSL AXI4-Stream index that caused the exception
DIZ Data storage - Zone protection
0 = Did not occur
1 = Occurred
S Data storage - Store instruction
0 = Did not occur
1 = Occurred
Reserved
DIZ Instruction storage - Zone protection
0 = Did not occur
1 = Occurred
Reserved
Reserved
S Data TLB miss - Store instruction
0 = Did not occur
1 = Occurred
Reserved
Reserved
and Table 2-13
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Chapter 2: MicroBlaze Architecture
Description
provides bit descriptions and reset values.
Reset Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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