Memory Architecture - Xilinx MicroBlaze Reference Manual

Memory Architecture

MicroBlaze is implemented with a Harvard memory architecture; instruction and data
accesses are done in separate address spaces. The instruction address space has a 32-bit
range (that is, handles up to 4GB of instructions). The data address space has a default 32-
bit range, and can be extended up to a 64-bit range (that is, handles from 4GB to 16EB of
data). The instruction and data memory ranges can be made to overlap by mapping them
both to the same physical memory. The latter is necessary for software debugging.
Both instruction and data interfaces of MicroBlaze are default 32 bits wide and use big
endian or little endian, bit-reversed format, depending on the selected endianness.
MicroBlaze supports word, halfword, and byte accesses to data memory.
Big endian format is only available when using the MMU in virtual or protected mode
( > 1) or when reorder instructions are enabled (
C_USE_MMU
Data accesses must be aligned (word accesses must be on word boundaries, halfword on
halfword boundaries), unless the processor is configured to support unaligned exceptions.
All instruction accesses must be word aligned.
MicroBlaze prefetches instructions to improve performance, using the instruction prefetch
buffer and (if enabled) instruction cache streams. To avoid attempts to prefetch instructions
beyond the end of physical memory, which may cause an instruction bus error or a
processor stall, instructions must not be located too close to the end of physical memory.
The instruction prefetch buffer requires 16 bytes margin, and using instruction cache
streams adds two additional cache lines (32, 64 or 128 bytes).
MicroBlaze does not separate data accesses to I/O and memory (it uses memory mapped
I/O). The processor has up to three interfaces for memory accesses:
• Local Memory Bus (LMB)
• Advanced eXtensible Interface (AXI4) for peripheral access
• Advanced eXtensible Interface (AXI4) or AXI Coherency Extension (ACE) for cache
access
The LMB memory address range must not overlap with AXI4 ranges.
The
C_ENDIANNESS
MicroBlaze has a single cycle latency for accesses to local memory (LMB) and for cache read
hits, except with
read hits require two clock cycles, and with
and halfword writes to LMB normally require two clock cycles.
The data cache write latency depends on
C_DCACHE_USE_WRITEBACK
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
parameter is always set to little endian.
set to 1 (Area), when data side accesses and data cache
C_AREA_OPTIMIZED
is set to 1, the write latency normally is one cycle (more if the
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Chapter 2: MicroBlaze Architecture
C_USE_REORDER_INSTR
set to 1, when byte writes
C_FAULT_TOLERANT
C_DCACHE_USE_WRITEBACK
= 1).
. When
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