Xilinx MicroBlaze Reference Manual page 237

msrclr
Read MSR and clear bits in MSR
msrclr
1 0 0 1 0 1
0 6
Description
Copies the contents of the special purpose register MSR into register rD.
Bit positions in the IMM value that are 1 are cleared in the MSR. Bit positions that are 0 in the
IMM value are left untouched.
When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged
for all IMM values except those only affecting C. This means that if the instruction is attempted
in User Mode (MSR[UM] = 1) in this case a Privileged Instruction exception occurs.
Pseudocode
if MSR[UM] = 1 and IMM
ESR[EC]
else
(rD)
(MSR)
Registers Altered
• rD
• MSR
• ESR[EC], in case a privileged instruction exception is generated
Latency
• 1 cycle
Notes
MSRCLR will affect the Carry bit immediately while the remaining bits will take effect one cycle
after the instruction has been executed. When clearing the IE bit, it is guaranteed that the
processor will not react to any interrupt for the subsequent instructions.
The value read from MSR may not include effects of the immediately preceding instruction
(dependent on pipeline stall behavior). An instruction that does not affect MSR must precede
the MSRCLR instruction to guarantee correct MSR value. This applies to both the value copied to
register rD and the changed MSR value itself.
The immediate values has to be less than 215 when C_USE_MMU >= 1 (User Mode), and less than
214 otherwise. Only bits 17 to 31 of the MSR can be cleared when C_USE_MMU >= 1 (User Mode),
and.bits 18 to 31 otherwise.
This instruction is only available when the parameter C_USE_MSR_INSTR is set to 1.
When clearing MSR[VM] the instruction must always be followed by a synchronizing branch
instruction, for example BRI 4.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
rD, Imm
rD 1 0 0 0 1 0
11
≠
0x4 then
←
00111
←
(MSR)
← ∧ (
(MSR) IMM))
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Chapter 5: MicroBlaze Instruction Set Architecture
Imm15
16 17 31
237
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