Xilinx MicroBlaze Reference Manual page 33

Table 2-18: Process Identifier Register (PID)
Bits Name
0:23 Reserved
24:31 PID
Zone Protection Register (ZPR)
The Zone Protection Register is used to override MMU memory protection defined in TLB
entries. It is controlled by the
is only implemented if
0 (Performance), and if the number of specified memory protection zones is greater than
zero (
C_MMU_ZONES
memory protection zones (
instructions, the ZPR is specified by setting Sa = 0x1001. The register is accessible
according to the memory management special registers parameter
Figure 2-13 illustrates the ZPR register and
values.
0 2 4 6
↑ ↑ ↑ ↑
ZP0 ZP1 ZP2 ZP3
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
↑
RESERVED
Figure 2-12: PID
Used to uniquely identify a software process during MMU
address translation.
Read/Write
C_USE_MMU
is greater than 1 (User Mode),
C_USE_MMU
> ). The implemented register bits depend on the number of specified
0
). When accessed with the MFS and MTS
C_MMU_ZONES
8 10 12 14
↑ ↑ ↑ ↑
ZP4 ZP5 ZP6 ZP7
Figure 2-13: ZPR
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Chapter 2: MicroBlaze Architecture
Description
configuration option on MicroBlaze. The register
Table 2-19 provides bit descriptions and reset
16 18 20 22
↑ ↑ ↑ ↑
ZP8 ZP9 ZP10 ZP11
24
↑
PID
Reset Value
0x00
is set to
C_AREA_OPTIMIZED
C_MMU_TLB_ACCESS
24 26 28 30
↑ ↑ ↑
ZP12 ZP13 ZP14 ZP15
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