Xilinx MicroBlaze Reference Manual page 130

Table 3-1: Summary of MicroBlaze Core I/O (Cont'd)
Signal
Sn_AXIS_TLAST
Sn_AXIS_TDATA
Sn_AXIS_TVALID
Sn_AXIS_TREADY
Interrupt
Interrupt_Address
Interrupt_Ack
Reset
Reset_Mode[0:1]
Clk
Ext_BRK
Ext_NM_BRK
MB_Halted
Dbg_Stop
Dbg_Intr
MB_Error
Sleep
Hibernate
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Interface I/O
S0_AXIS.. I
S15_AXIS
S0_AXIS.. I
S15_AXIS
S0_AXIS.. I
S15_AXIS
S0_AXIS.. O
S15_AXIS
Core I
Core I
1
Core O
1
Core I
Core I
Core I
Core I
Core I
Core O
Core I
Core O
Core O
Core O
Core O
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Chapter 3: MicroBlaze Signal Interface Description
Description
Slave interface input AXI4 channels
write last
Slave interface input AXI4 channels
write data
Slave interface input AXI4 channels
write valid
Slave interface output AXI4 channels
write ready
Interrupt. The signal is synchronized to
parameter
C_ASYNC_INTERRUPT
Interrupt vector address
Interrupt acknowledge
Core reset, active high. Should be held for at
least 1 clock cycle.
Clk
Reset mode. Sampled when Reset is active.
SeeTable 3-2 for details.
2
Clock
Break signal from MDM
Non-maskable break signal from MDM
Pipeline is halted, either via the Debug Interface,
by setting or by setting
Dbg_Stop,
to 10.
Reset_Mode[0:1]
Unconditionally force pipeline to halt as soon as
possible. Rising-edge detected pulse that should
be held for at least 1 Clk clock cycle. The signal
only has any effect when C_DEBUG_ENABLED is
greater than 0.
Debug interrupt output, set when a Performance
Monitor counter overflows, available when
C_DEBUG_ENABLED is set to 2 (Extended).
Pipeline is halted due to a missed exception,
when C_FAULT_TOLERANT is set to 1.
MicroBlaze is in sleep mode after executing a
SLEEP instruction or by setting
to 10, all external accesses are completed, and
the pipeline is halted.
MicroBlaze is in sleep mode after executing a
HIBERNATE instruction, all external accesses are
completed, and the pipeline is halted.
if the
Clk
is set.
Reset_Mode[0:1]
130
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