Xilinx MicroBlaze Reference Manual page 43

Table 2-29: Processor Version Register 5 (PVR5) (Cont'd)
Bits Name
18 Reserved
19:21 DCV
22:23 Reserved
24 DFTL
25 DCDW
26 AXI4DC
27:31 Reserved
Table 2-30: Processor Version Register 6 (PVR6)
Bits Name
0:31 ICBA
Table 2-31: Processor Version Register 7 (PVR7)
Bits Name
0:31 ICHA
Table 2-32: Processor Version Register 8 (PVR8)
Bits
0:C_ADDR_SIZE-1
Table 2-33: Processor Version Register 9 (PVR9)
Bits
0:C_ADDR_SIZE-1
Table 2-34: Processor Version Register 10 (PVR10)
Bits Name
0:7 ARCH
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Description
Data cache victims
Data cache tag uses distributed RAM
Data cache data width
Data Cache AXI interface uses AXI4 protocol,
with support for exclusive access
Description
Instruction Cache Base Address
Description
Instruction Cache High Address
Name Description
DCBA Data Cache Base Address
Name Description
DCHA Data Cache High Address
Description
Target architecture:
0xF = Virtex-7, Defence Grade Virtex-7 Q
0x10 = Kintex™-7, Defence Grade Kintex-7 Q
0x11 = Artix™-7, Automotive Artix-7,
Defence Grade Artix-7 Q
0x12 = Zynq™-7000, Automotive Zynq-7000,
Defence Grade Zynq-7000 Q
0x13 = UltraScale™ Virtex
0x14 = UltraScale Kintex
0x15 = UltraScale+ Zynq
0x16 = UltraScale+ Virtex
0x17 = UltraScale+ Kintex
www.xilinx.com
Chapter 2: MicroBlaze Architecture
Value
0
0-3: C_DCACHE_VICTIMS = 0,2,4,8
0
C_DCACHE_FORCE_TAG_LUTRAM
C_DCACHE_DATA_WIDTH > 0
C_M_AXI_DC_EXCLUSIVE_ACCESS
0
Value
C_ICACHE_BASEADDR
Value
C_ICACHE_HIGHADDR
Value
C_DCACHE_BASEADDR
Value
C_DCACHE_HIGHADDR
Value
Defined by parameter C_FAMILY
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