Xilinx MicroBlaze Reference Manual page 138

Table 3-5: AXI Interface Signal Definitions
Interface
M_AXI_DC C_M_AXI_DC_AWCACHE
M_ACE_DC
C_M_AXI_DC_ARPROT
C_M_AXI_DC_AWPROT
C_M_AXI_DC_ARQOS
C_M_AXI_DC_AWQOS
The data cache interface (M_AXI_DC or M_ACE_DC) address width can range from 32 - 64
bits, depending on the value of the parameter C_ADDR_SIZE.
Please refer to the AMBA AXI and ACE Protocol Specification
details.
Stream Interfaces
The MicroBlaze AXI4-Stream interfaces (M0_AXIS..M15_AXIS, S0_AXIS..S15_AXIS) are
implemented as 32-bit masters and slaves. Please refer to the AMBA 4 AXI4-Stream Protocol
Specification, Version 1.0
Write Operation
A write to the stream interface is performed by MicroBlaze using one of the put or putd
instructions. A write operation transfers the register contents to an output AXI4 interface.
The transfer is completed in a single clock cycle for blocking mode writes (put and cput
instructions) as long as the interface is not busy. If the interface is busy, the processor stalls
until it becomes available. The non-blocking instructions (with prefix n), always complete in
a single clock cycle even if the interface is busy. If the interface was busy, the write is
inhibited and the carry bit is set in the MSR.
The control instructions (with prefix c) set the AXI4-Stream TLAST output, to '1', which is
used to indicate the boundary of a packet.
Read Operation
A read from the stream interface is performed by MicroBlaze using one of the get or getd
instructions. A read operations transfers the contents of an input AXI4 interface to a general
purpose register. The transfer is typically completed in 2 clock cycles for blocking mode
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Chapter 3: MicroBlaze Signal Interface Description
Signal
Memory Type, normal access:
• Write-back Read and Write-allocate (1111)
Memory Type, exclusive access:
• Normal Non-cacheable Non-bufferable (0010)
Access Permission:
• Unprivileged, secure data access (000) if input signal
Non_Secure[2] = 0
• Unprivileged, non-secure data access (010) if input signal
Non_Secure[2] = 1
Quality of Service, read access:
• Priority 12 ((1100)
Quality of Service, write access:
• Priority 8 (1000)
(ARM IHI 0051A) document for further details.
www.xilinx.com
Description
(ARM IHI 0022E) document for
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