Xilinx MicroBlaze Reference Manual page 71

Hardware Breaks
Hardware breaks are performed by asserting the external break signal (that is, the
and
Ext_NM_BRK
while the instruction in the decode stage is replaced by a branch to the break vector
(address
C_BASE_VECTORS
instruction in the decode stage at the time of the break) is automatically loaded into
general purpose register R16. MicroBlaze also sets the Break In Progress (
Machine Status Register (MSR).
A normal hardware break (that is, the
and MSR[EIP] are set to 0 (that is, there is no break or exception in progress). The Break In
Progress flag disables interrupts. A non-maskable break (that is, the
is always handled immediately.
The BIP bit in the MSR is automatically cleared when executing the
The signal must be kept asserted until the break has occurred, and deasserted
Ext_BRK
before the RTBD instruction is executed. The
clock cycle.
Software Breaks
To perform a software break, use the
MicroBlaze Instruction Set Architecture
As a special case, when C_USE_DEBUG is set, and "
breakpoint is signaled to the debugger, e.g. the Xilinx System Debugger (XSDB) tool,
irrespective of the value of
Latency
The time it takes MicroBlaze to enter a break service routine from the time the break occurs
depends on the instruction currently in the execution stage and the latency to the memory
storing the break vector.
Equivalent Pseudocode
←
r16 PC
←
PC C_BASE_VECTORS + 0x00000018
←
MSR[BIP]
←
MSR[UMS]
Reservation
Interrupt
MicroBlaze supports one external interrupt source (connected to the
The processor only reacts to interrupts if the Interrupt Enable (IE) bit in the Machine Status
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
input ports). On a break, the instruction in the execution stage completes
+ 0x18). The break return address (the PC associated with the
Ext_BRK
brk
C_BASE_VECTORS
1
←
MSR[UM], MSR[UM] 0, MSR[VMS]
←
0
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Chapter 2: MicroBlaze Architecture
input port) is only handled when MSR[BIP]
signal must only be asserted one
Ext_NM_BRK
and instructions. Refer to
brki
for detailed information on software breaks.
brki rD, 0x18"
.
←
MSR[VM], MSR[VM]
Ext_BRK
) flag in the
BIP
input port)
Ext_NM_BRK
instruction.
RTBD
Chapter 5,
is executed, a software
←
0
input port).
Interrupt
71
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