Xilinx MicroBlaze Reference Manual page 25

Table 2-9: Machine Status Register (MSR) (Cont'd)
Bits Name
20 UM
21 PVR
22 EIP
23 EE
24 DCE
25 DZO
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
User Mode
0 = Privileged Mode, all instructions are allowed
1 = User Mode, certain instructions are not allowed
Only available when configured with an MMU
(if C_USE_MMU > 0 and C_AREA_OPTIMIZED = 0)
Read/Write
Processor Version Register exists
0 = No Processor Version Register
1 = Processor Version Register exists
Read only
Exception In Progress
0 = No hardware exception in progress
1 = Hardware exception in progress
Only available if configured with exception support
(C_*_EXCEPTION or C_USE_MMU > 0)
Read/Write
Exception Enable
0 = Hardware exceptions disabled
1 = Hardware exceptions enabled
Only available if configured with exception support
( or
C_*_EXCEPTION C_USE_MMU > 0
Read/Write
Data Cache Enable
0 = Data Cache disabled
1 = Data Cache enabled
Only available if configured to use data cache
( = 1)
C_USE_DCACHE
Read/Write
Division by Zero or Division Overflow
0 = No division by zero or division overflow has occurred
1 = Division by zero or division overflow has occurred
Only available if configured to use hardware divider
( = 1)
C_USE_DIV
Read/Write
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Chapter 2: MicroBlaze Architecture
Description
1
)
2
Reset Value
0
Based on
parameter
C_PVR
0
0
0
0
25
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