Xilinx MicroBlaze Reference Manual page 131

Table 3-1: Summary of MicroBlaze Core I/O (Cont'd)
Signal
Suspend
Wakeup[0:1]
Dbg_Wakeup
Pause
Pause_Ack
Dbg_Continue
Non_Secure[0:3]
Lockstep_...
Dbg_...
Trace_...
1. Only used with C_USE_INTERRUPT = 2, for low-latency interrupt support.
2. MicroBlaze is a synchronous design clocked with the Clk signal, except for hardware debug logic, which is clocked
with the Dbg_Clk signal. If hardware debug logic is not used, there is no minimum frequency limit for Clk. However,
if hardware debug logic is used, there are signals transferred between the two clock regions. In this case Clk must
have a higher frequency than Dbg_Clk.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Chapter 3: MicroBlaze Signal Interface Description
Interface I/O
MicroBlaze is in sleep mode after executing a
Core O
SUSPEND instruction, all external accesses are
completed, and the pipeline is halted.
Wake MicroBlaze from sleep mode when either
Core I
or both bits are set to 1. Ignored if MicroBlaze is
not in sleep mode. The signals are individually
synchronized to
C_ASYNC_WAKEUP[0:1]
Debug request that external logic should wake
Core O
MicroBlaze from sleep mode with the Wakeup
signal, to allow debug access. Synchronous to
Dbg_Clk
When this signal is set MicroBlaze pipeline will
Core I
be paused after completing all ongoing bus
accesses, and the
When this signal is cleared again MicroBlaze will
continue normal execution where it was paused.
MicroBlaze is in pause mode after the
Core O
input signal has been set.
Debug request that external logic should clear
Core O
the
Pause
Determines whether AXI accesses are non-
Core I
secure or secure. The default value is binary
0000, setting all interfaces to be secure.
Bit 0 = M_AXI_DP
Bit 1 = M_AXI_IP
Bit 2 = M_AXI_DC
Bit 3 = M_AXI_IC
Lockstep signals for high integrity applications.
Core IO
See Table 3-12
Debug signals from MDM. See
Core IO
details.
Trace signals for real time HW analysis. See
Core O
Table 3-15
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Description
according to the parameter
Clk
.
.
signal will be set.
Pause_Ack
signal, to allow debug access.
for details.
for details.
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Pause
Table 3-14 for
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