Xilinx MicroBlaze Reference Manual page 56

• Data Shadow TLB—The DTLB contains data page-translation entries and is fully
associative. The page-translation entries stored in the DTLB represent the most-recently
accessed data-page translations from the UTLB. The DTLB is used to minimize
contention between data translation and UTLB-update operations. The initialization
and management of the DTLB is controlled completely by hardware and is transparent
to software.
Figure 2-19 provides the translation flow for TLB.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Generate I-side
Effective Address
Translation Disabled Translation Enabled
(MSR[VM]=0) (MSR[VM]=1)
Perform ITLB
No Translation
ITLB Hit
Extract Real
Address from ITLB
Continue I-cache
Access
Extract Real
Address from UTLB
Route Address Route Address
to ITLB
Figure 2-19: TLB Address Translation Flow
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Translation Enabled
(MSR[VM]=1)
Perform DTLB
Look-Up
Look-Up
ITLB Miss DTLB Miss
Perform UTLB
Look-Up
UTLB Hit UTLB Miss
to DTLB
Generate D-side
Effective Address
Translation Disabled
(MSR[VM]=0)
No Translation
DTLB Hit
Extract Real
Address from DTLB
Continue I-cache
or D-cache
Access
I-Side TLB Miss
or
D-Side TLB Miss
Exception
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