Xilinx MicroBlaze Reference Manual page 183

andi
Logial AND with Immediate
andi rD, rA, IMM
1 0 1 0 0 1
0 6
Description
The contents of register rA are ANDed with the value of the IMM field, sign-extended to 32 bits; the
result is placed into register rD.
Pseudocode
←
(rD) (rA)
Registers Altered
• rD
Latency
1 cycle
Note
By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to 32 bits to use
as the immediate operand. This behavior can be overridden by preceding the Type B instruction with
an imm instruction. See the instruction
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
rD rA
1
1
∧
sext(IMM)
"imm," page 222
www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
IMM
1
6
for details on using 32-bit immediate values.
3
1
183
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