Xilinx MicroBlaze Reference Manual page 232

lwx
Load Word Exclusive
lwx rD, rA, rB
1 1 0 0 1 0
0 6
Description
Loads a word (32 bits) from the word aligned memory location that results from adding the contents
of registers rA and rB. The data is placed in register rD, and the reservation bit is set. If an AXI4
interconnect with exclusive access enabled is used, and the interconnect response is not EXOKAY, the
carry flag (MSR[C]) is set; otherwise the carry flag is cleared.
A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry
corresponding to the address is not found in the TLB.
A data storage exception occurs if access is prevented by a no-access-allowed zone protection. This
only applies to accesses with user mode and virtual protected mode enabled.
An unaligned data access exception will not occur, even if the two least significant bits in the address
are not zero.
A data bus exception can occur when an AXI4 interconnect with exclusive access enabled is used, and
the interconnect response is not EXOKAY, which means that an exclusive access cannot be handled.
Enabling AXI exclusive access ensures that the operation is protected from other bus masters, but
requires that the addressed slave supports exclusive access. When exclusive access is not enabled,
only the internal reservation bit is used. Exclusive access is enabled using the two parameters
C_M_AXI_DP_EXCLUSIVE_ACCESS and C_M_AXI_DC_EXCLUSIVE_ACCESS for the peripheral and cache
interconnect, respectively.
Pseudocode
←
Addr (rA) + (rB)
if TLB_Miss(Addr) and MSR[VM] = 1 then
←
ESR[EC]
MSR[UMS]
else if Access_Protected(Addr) and MSR[UM] = 1 and MSR[VM] = 1 then
←
ESR[EC]
←
MSR[UMS]
else if AXI_Exclusive(Addr) and AXI_Response
←
ESR[EC]
←
MSR[UMS]
else
←
(rD) Mem(Addr); Reservation
if AXI_Exclusive(Addr) and AXI_Response
←
MSR[C]
else
←
MSR[C]
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
rD rA
11
←
10010;ESR[S] 0
← ←
MSR[UM]; MSR[VMS]
←
10000;ESR[S] 0; ESR[DIZ]
←
MSR[UM]; MSR[VMS]
←
00100;ESR[ECC] 0;
←
MSR[UM]; MSR[VMS]
1
0
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Chapter 5: MicroBlaze Instruction Set Architecture
rB 1 0 0 0 0 0 0 0 0 0 0
16 21
←
MSR[VM]; MSR[UM]
←
1
←
MSR[VM]; MSR[UM] 0; MSR[VM]
≠
EXOKAY and MSR[EE] then
←
MSR[VM]; MSR[UM] 0; MSR[VM]
←
1;
≠
EXOKAY then
←
0; MSR[VM] 0
←
0
←
0
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