Pipeline Architecture - Xilinx MicroBlaze Reference Manual

Pipeline Architecture

MicroBlaze instruction execution is pipelined. For most instructions, each stage takes one
clock cycle to complete. Consequently, the number of clock cycles necessary for a specific
instruction to complete is equal to the number of pipeline stages, and one instruction is
completed on every cycle. A few instructions require multiple clock cycles in the execute
stage to complete. This is achieved by stalling the pipeline.
When executing from slower memory, instruction fetches may take multiple cycles. This
additional latency directly affects the efficiency of the pipeline. MicroBlaze implements an
instruction prefetch buffer that reduces the impact of such multi-cycle instruction memory
latency. While the pipeline is stalled by a multi-cycle instruction in the execution stage, the
prefetch buffer continues to load sequential instructions. When the pipeline resumes
execution, the fetch stage can load new instructions directly from the prefetch buffer
instead of waiting for the instruction memory access to complete. If instructions are
modified during execution (e.g. with self-modifying code), the prefetch buffer should be
emptied before executing the modified instructions, to ensure that it does not contain the
old unmodified instructions. The recommended way to do this is using an MBAR
instruction, although it is also possible to use a synchronizing branch instruction, for
example BRI 4.
Three Stage Pipeline
With
C_AREA_OPTIMIZED
hardware cost: Fetch, Decode, and Execute.
instruction 1
instruction 2
instruction 3
Five Stage Pipeline
With
C_AREA_OPTIMIZED
maximize performance: Fetch (IF), Decode (OF), Execute (EX), Access Memory (MEM), and
Writeback (WB).
instruction 1
instruction 2
instruction 3
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
set to 1 (Area), the pipeline is divided into three stages to minimize
cycle1 cycle2 cycle3
Fetch Decode Execute
Fetch Decode
Fetch
set to 0 (Performance), the pipeline is divided into five stages to
cycle1 cycle2 cycle3 cycle4
IF OF EX MEM
IF OF
IF
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Chapter 2: MicroBlaze Architecture
cycle4 cycle5 cycle6
Execute Execute Execute
Decode Stall
cycle5 cycle6 cycle7
WB
EX MEM MEM MEM
OF EX Stall Stall
cycle7
Stall Execute
cycle8 cycle9
WB
MEM WB
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