Xilinx MicroBlaze Reference Manual page 70

Should an Instruction Bus Exception, Illegal Opcode Exception or Data Bus Exception occur
when
C_FAULT_TOLERANT
MSR[EE] cleared), the pipeline is halted, and the external signal
Imprecise Exceptions
Normally all exceptions in MicroBlaze are precise, meaning that any instructions in the
pipeline after the instruction causing an exception are invalidated, and have no effect.
When
C_IMPRECISE_EXCEPTIONS
Exception caused by ECC errors in LMB memory is not precise, meaning that a subsequent
memory access instruction in the pipeline may be executed. If this behavior is acceptable,
the maximum frequency can be improved by setting this parameter to 1.
Equivalent Pseudocode
←
ESR[DS]
if ESR[DS] then
←
BTR branch target PC
if MMU exception then
if branch preceded by IMM then
r17
else
r17
else
r17
else if MMU exception then
if instruction preceded by IMM then
←
r17
else
←
r17
else
←
r17 PC + 4
←
PC C_BASE_VECTORS + 0x00000020
←
MSR[EE]
←
MSR[UMS]
←
ESR[EC]
←
ESR[ESS]
←
EAR exception specific value
←
FSR exception specific value
Reservation
Breaks
There are two kinds of breaks:
• Hardware (external) breaks
• Software (internal) breaks
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
is set to 1, and an exception is in progress (i.e. MSR[EIP] set and
is set to 1 (
exception in delay slot
←
PC - 8
←
PC - 4
←
invalid value
PC - 4
PC
←
0, MSR[EIP] 1
←
MSR[UM], MSR[UM]
exception specific value
exception specific value
←
0
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Chapter 2: MicroBlaze Architecture
) an Instruction Bus Exception or Data Bus
ECC
←
0, MSR[VMS] MSR[VM], MSR[VM]
is set.
MB_Error
←
0
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