Xilinx MicroBlaze Reference Manual page 266

sh
Store Halfword
sh rD, rA, rB
shr rD, rA, rB
shea rD, rA, rB
1 1 0 1 0 1
0 6
Description
Stores the contents of the least significant halfword of register rD, into the halfword aligned memory
location that results from adding the contents of registers rA and rB.
If the R bit is set, a halfword reversed memory location is used and the two bytes in the halfword are
reversed, storing data with the opposite endianness of the endianness defined by the E bit (if virtual
protected mode is enabled).
If the EA bit is set, an extended address is used, formed by concatenating rA and rB instead of adding
them.
A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry
corresponding to the address is not found in the TLB.
A data storage exception occurs if virtual protected mode is enabled, and access is prevented by no-
access-allowed or read-only zone protection. No-access-allowed can only occur in user mode.
An unaligned data access exception occurs if the least significant bit in the address is not zero.
Pseudocode
if EA = 1 then
← (
Addr rA) & (rB)
else
←
Addr (rA) + (rB)
if TLB_Miss(Addr) and MSR[VM] = 1 then
←
ESR[EC]
MSR[UMS]
else if Access_Protected(Addr) and MSR[VM] = 1 then
←
ESR[EC]
←
MSR[UMS]
else if Addr[31]
←
ESR[EC]
else
Mem(Addr)
Registers Altered
• MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if a TLB miss exception or a data storage
exception is generated
• ESR[EC], ESR[S], if an exception is generated
• ESR[DIZ], if a data storage exception is generated
• ESR[W], ESR[Rx], if an unaligned data access exception is generated
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
rD rA
11
←
10010;ESR[S] 1
← ←
MSR[UM]; MSR[VMS]
←
10000;ESR[S] 1; ESR[DIZ]
←
MSR[UM]; MSR[VMS]
≠
0 then
←
00001; ESR[W] 0; ESR[S]
←
(rD)[16:31]
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Chapter 5: MicroBlaze Instruction Set Architecture
rB 0 R 0 EA 0 0 0 0 0 0 0
16 21
←
MSR[VM]; MSR[UM] 0; MSR[VM]
←
No-access-allowed
←
MSR[VM]; MSR[UM] 0; MSR[VM]
← ←
1; ESR[Rx]
31
←
0
←
0
rD
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