Xilinx MicroBlaze Reference Manual page 127

Table 3-1: Summary of MicroBlaze Core I/O (Cont'd)
Signal
M_AXI_DC_ACREADY
M_AXI_DC_CRREADY
M_AXI_DC_CRVALID
M_AXI_DC_CRRESP
M_AXI_DC_CDVALID
M_AXI_DC_CDREADY
M_AXI_DC_CDDATA
M_AXI_DC_CDLAST
M_AXI_IC_AWID
M_AXI_IC_AWADDR
M_AXI_IC_AWLEN
M_AXI_IC_AWSIZE
M_AXI_IC_AWBURST
M_AXI_IC_AWLOCK
M_AXI_IC_AWCACHE
M_AXI_IC_AWPROT
M_AXI_IC_AWQOS
M_AXI_IC_AWVALID
M_AXI_IC_AWREADY
M_AXI_IC_AWUSER
M_AXI_IC_AWDOMAIN
M_AXI_IC_AWSNOOP
M_AXI_IC_AWBAR
M_AXI_IC_WDATA
M_AXI_IC_WSTRB
M_AXI_IC_WLAST
M_AXI_IC_WVALID
M_AXI_IC_WREADY
M_AXI_IC_WUSER
M_AXI_IC_BID
M_AXI_IC_BRESP
M_AXI_IC_BVALID
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Chapter 3: MicroBlaze Signal Interface Description
Interface I/O
Master Snoop ready
M_ACE_DC O
Slave Snoop response ready
M_ACE_DC I
Master Snoop response valid
M_ACE_DC O
Master Snoop response
M_ACE_DC O
Master Snoop data valid
M_ACE_DC O
Slave Snoop data ready
M_ACE_DC I
Master Snoop data
M_ACE_DC O
Master Snoop data last
M_ACE_DC O
Master Write address ID
M_AXI_IC O
Master Write address
M_AXI_IC O
Master Burst length
M_AXI_IC O
Master Burst size
M_AXI_IC O
Master Burst type
M_AXI_IC O
Master Lock type
M_AXI_IC O
Master Cache type
M_AXI_IC O
Master Protection type
M_AXI_IC O
Master Quality of Service
M_AXI_IC O
Master Write address valid
M_AXI_IC O
Slave Write address ready
M_AXI_IC I
Master Write address user signals
M_AXI_IC O
Master Write address domain
M_ACE_IC O
Master Write address snoop
M_ACE_IC O
Master Write address barrier
M_ACE_IC O
Master Write data
M_AXI_IC O
Master Write strobes
M_AXI_IC O
Master Write last
M_AXI_IC O
Master Write valid
M_AXI_IC O
Slave Write ready
M_AXI_IC I
Master Write user signals
M_AXI_IC O
Slave Response ID
M_AXI_IC I
Slave Write response
M_AXI_IC I
Slave Write response valid
M_AXI_IC I
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