Xilinx MicroBlaze Reference Manual page 80

With the write-back protocol, a store to an address within the cacheable range always
updates the cached data. If the target address word is not in the cache (that is, the access
is a cache miss), and the location in the cache contains data that has not yet been written
to memory (the cache location is dirty), the old data is written over the data AXI4 interface
(M_AXI_DC) to external memory before updating the cache with the new data. If only a
single word needs to be written, a single word write is used, otherwise a burst write is used.
For byte or halfword stores, in case of a cache miss, the address is first requested over the
data AXI4 interface, while a word store only updates the cache.
With the write-through protocol, a store to an address within the cacheable range
generates an equivalent byte, halfword, or word write over the data AXI4 interface to
external memory. The write also updates the cached data if the target address word is in the
cache (that is, the write is a cache hit). A write cache-miss does not load the associated
cache line into the cache.
Provided that the cache is enabled a load from an address within the cacheable range
triggers a check to determine if the requested data is currently cached. If it is (that is, on a
cache hit) the requested data is retrieved from the cache. If not (that is, on a cache miss) the
address is requested over the data AXI4 interface using a burst read, and the processor
pipeline stalls until the cache line associated to the requested address is returned from the
external memory controller.
The parameter
entire cache line (128, 256 or 512 bits), or 512 bits.
When
C_FAULT_TOLERANT
occurs if a parity error is detected in the tag or data Block RAM.
All types of accesses issued by the data cache AXI4 interface are summarized in
Data Cache Interface Accesses
Table 2-39:
Policy
Write-
through
Write-back
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
C_DCACHE_DATA_WIDTH
is set to 1 and write-through protocol is used, a cache miss also
State Direction
Burst for 32-bit interface non-exclusive access
Cache Read
Enabled
and exclusive access with ACE enabled, single ac-
cess otherwise
Write Single access
Burst for 32-bit interface exclusive access with
Cache Read
Disabled
ACE enabled, single access otherwise
Single access
Write
Cache Read Burst for 32-bit interface, single access otherwise
Enabled
Write Burst for 32-bit interface cache lines with more
than one valid word, a single access otherwise
Cache Read Burst for 32-bit interface non-exclusive access,
Disabled
discarding all but the desired data, a single ac-
cess otherwise
Write Single access
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Chapter 2: MicroBlaze Architecture
determines the bus data width, either 32 bits, an
Access Type
Table 2-39.
80
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