Xilinx MicroBlaze Reference Manual page 239

mts
Move To Special Purpose Register
mts
1 0 0 1 0 1 0 0 0 0 0
0 6
Description
Copies the contents of register rD into the special purpose register rS. The special purpose
registers TLBLO and TLBHI are used to copy to the Unified TLB entry indexed by TLBX.
When MicroBlaze is configured to use an MMU (C_USE_MMU >= 1) this instruction is privileged.
This means that if the instruction is attempted in User Mode (MSR[UM] = 1) a Privileged
Instruction exception occurs.
With low-latency interrupt mode (C_USE_INTERRUPT = 2), the Interrupt_Ack output port is set to
11 if the MSR{IE] bit is set by executing this instruction.
Pseudocode
if MSR[UM] = 1 then
ESR[EC] ← 00111
else
switch (rS)
case 0x0001 : MSR
case 0x0007 : FSR
case 0x0800 : SLR
case 0x0802 : SHR
case 0x1000 : PID
case 0x1001 : ZPR
case 0x1002 : TLBX
case 0x1003 : TLBLO ← (rA)
case 0x1004 : TLBHI ← (rA)
case 0x1005 : TLBSX ← (rA)
if (rS) = 0x0001 and (rA) & 2
Interrupt_Ack
Registers Altered
• rS
• ESR[EC], in case a privileged instruction exception is generated
Latency
• 1 cycle
Notes
When writing MSR using MTS, all bits take effect one cycle after the instruction has been executed.
An MTS instruction writing MSR should never be followed back-to-back by an instruction that uses
the MSR content. When clearing the IE bit, it is guaranteed that the processor will not react to any
interrupt for the subsequent instructions. When setting the EIP or BIP bit, it is guaranteed that the
processor will not react to any interrupt or normal hardware break for the subsequent instructions.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
rS, rA
rA
11
← (rA)
← (rA)
← (rA)
← (rA)
← (rA)
← (rA)
← (rA)
← 11
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Chapter 5: MicroBlaze Instruction Set Architecture
1 1
16 18
rS
31
239
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