Xilinx MicroBlaze Reference Manual page 247

ori
Logical OR with Immediate
ori
1 0 1 0 0 0
0 6
Description
The contents of register rA are ORed with the extended IMM field, sign-extended to 32 bits; the
result is placed into register rD.
Pseudocode
←
(rD)
Registers Altered
• rD
Latency
• 1 cycle
Note
By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to 32 bits
to use as the immediate operand. This behavior can be overridden by preceding the Type B
instruction with an imm instruction. See the instruction
bit immediate values.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
rD, rA, IMM
rD rA
1
1
∨
(rA) sext(IMM)
www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
IMM
1
6
"imm," page 222
3
1
for details on using 32-
247
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