Xilinx MicroBlaze Reference Manual page 271

srl
Shift Right Logical
srl rD, rA
1 0 0 1 0 0
0 6
Description
Shifts logically the contents of register rA, one bit to the right, and places the result in rD. A zero is
shifted in the shift chain and placed in the most significant bit of rD. The least significant bit coming
out of the shift chain is placed in the Carry flag.
Pseudocode
←
(rD)[0]
(rD)[1:31]
←
MSR[C] (rA)[31]
Registers Altered
• rD
• MSR[C]
Latency
• 1 cycle
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
rD rA
1
1
0
← (
rA)[0:30]
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Chapter 5: MicroBlaze Instruction Set Architecture
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1
1
6
3
1
271
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