Xilinx MicroBlaze Reference Manual page 182

and
Logical AND
and rD, rA, rB
1 0 0 0 0 1
0 6
Description
The contents of register rA are ANDed with the contents of register rB; the result is placed into
register rD.
Pseudocode
← (rA) ∧ (rB)
(rD)
Registers Altered
• rD
Latency
1 cycle
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
rD rA
1
1
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Chapter 5: MicroBlaze Instruction Set Architecture
rB 0 0 0 0 0 0 0 0 0 0 0
1 2
6 1
3
1
182
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