Xilinx MicroBlaze Reference Manual page 94

Table 2-44: Performance Counter Status Register (PCSR)
Bits Name
1 Overflow
0 Full
Performance Counter Data Read Register
The Performance Counter Data Read Register (PCDRR) reads the sampled values of the
counters. To read the values of all configured counters, the register should be read
repeatedly. This register is a read-only register. Issuing a write request to the register does
nothing.
Since a counter can have more than 32 bits, depending on the configuration, the register
may need to be read repeatedly to retrieve all information for a particular counter. This is
detailed in Table
31
Table 2-45: Performance Counter Data Read Register (PCDRR)
Bits Name
31:0 Item
Table 2-46: Performance Counter Data Items
Counter Type
Event Counter
Latency Counter
Event Counter
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
This bit is set when the counter has counted past its maximum value
This bit is set when a new latency counter event is started before the
previous event has finished. This indicates that the accuracy of the
measured values is reduced.
2-46.
Figure 2-29: Performance Counter Data Read Register
Sampled counter value item
Item
C_DEBUG_COUNTER_WIDTH = 32
The number of times the event occurred
1
1 The number of times the event occurred
2 The sum of each event latency
3 The sum of each event latency squared
31:16 Minimum measured latency, 16 bits
4
15:0 Maximum measured latency, 16 bits
C_DEBUG_COUNTER_WIDTH = 48
1 31:16 0x0000
15:0 The number of times the event occurred, 16 most significant bits
2 The number of times the event occurred, 32 least significant bits
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Chapter 2: MicroBlaze Architecture
Description
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Item
Description
Description
Reset Value
0
0
0
Reset Value
0
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