Xilinx MicroBlaze Reference Manual page 40

Table 2-24: Processor Version Register 0 (PVR0) (Cont'd)
Bits Name
9 BTC
10 ENDI
11 FT
12 SPROT
13 REORD
14:15 Reserved
16:23 MBV
24:31 USR1
Table 2-25: Processor Version Register 1 (PVR1)
Bits Name
0:31 USR2
Table 2-26: Processor Version Register 2 (PVR2)
Bits Name
0 DAXI
1 DLMB
2 IAXI
3 ILMB
4 IRQEDGE
5 IRQPOS
6 CEEXC
7:8 Reserved
9 Reserved
10 ACE
11 AXI4DP
12 FSL
13 FSLEXC
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Description
Use branch target cache
Selected endianness:
Always 1 = Little endian
Implement fault tolerant features
Use stack protection
Implement reorder instructions
MicroBlaze release version code
0x19 = v8.40.b 0x20 = v9.3
0x1B = v9.0 0x21 = v9.4
0x1D = v9.1 0x22 = v9.5
0x1F = v9.2 0x23 = v9.6
User configured value 1
Description
User configured value 2
Description
Data side AXI4 or ACE in use
Data side LMB in use
Instruction side AXI4 or ACE in use
Instruction side LMB in use
Interrupt is edge triggered
Interrupt edge is positive
Generate bus exceptions for ECC
correctable errors in LMB memory
Use ACE interconnect
Data Peripheral AXI interface uses AXI4
protocol, with support for exclusive access
Use extended AXI4-Stream instructions
Generate exception for AXI4-Stream
control bit mismatch
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Chapter 2: MicroBlaze Architecture
Value
C_USE_BRANCH_TARGET_CACHE
C_ENDIANNESS
C_FAULT_TOLERANT
C_USE_STACK_PROTECTION
C_USE_REORDER_INSTR
0
Release Specific
C_PVR_USER1
Value
C_PVR_USER2
Value
C_D_AXI
C_D_LMB
C_I_AXI
C_I_LMB
C_INTERRUPT_IS_EDGE
C_EDGE_IS_POSITIVE
C_ECC_USE_CE_EXCEPTION
0
1
C_INTERCONNECT = 3 (ACE)
C_M_AXI_DP_EXCLUSIVE_ACCESS
C_USE_EXTENDED_FSL_INSTR
C_FSL_EXCEPTION
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