Xilinx MicroBlaze Reference Manual page 241

mul
Multiply
mul
0 1 0 0 0 0
0 6
Description
Multiplies the contents of registers rA and rB and puts the result in register rD. This is a 32-bit by
32-bit multiplication that will produce a 64-bit result. The least significant word of this value is
placed in rD. The most significant word is discarded.
Pseudocode
←
(rD)
Registers Altered
• rD
Latency
• 1 cycle with
• 3 cycles with
Note
This instruction is only valid if the target architecture has multiplier primitives, and if present, the
MicroBlaze parameter C_USE_HW_MUL is greater than 0.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
rD, rA, rB
rD rA
1
1
×
LSW( (rA) (rB) )
C_AREA_OPTIMIZED
C_AREA_OPTIMIZED
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Chapter 5: MicroBlaze Instruction Set Architecture
rB 0 0 0 0 0 0 0 0 0 0 0
1 2
6 1
=0
=1
3
1
241
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