Xilinx MicroBlaze Reference Manual page 290

Table A-10: Parameter Configurations (Cont'd)
C_MMU_TLB_ACCESS
C_MMU_ZONES
C_NUMBER_OF_PC_BRK
C_NUMBER_OF_RD_ADDR_BRK
C_NUMBER_OF_WR_ADDR_BRK
C_OPCODE_0x0_ILLEGAL
C_PVR
C_UNALIGNED_EXCEPTIONS
C_USE_BARREL
C_USE_DCACHE
C_USE_DIV
C_USE_EXTENDED_FSL_INSTR
C_USE_FPU
C_USE_HW_MUL
C_USE_ICACHE
C_USE_MMU
C_USE_MSR_INSTR
C_USE_PCMP_INSTR
C_USE_REORDER_INSTR
C_USE_BRANCH_TARGET_CACHE
C_BRANCH_TARGET_CACHE_SIZE
C_ICACHE_STREAMS
C_ICACHE_VICTIMS
C_DCACHE_VICTIMS
C_ICACHE_FORCE_TAG_LUTRAM
C_DCACHE_FORCE_TAG_LUTRAM
C_ICACHE_ALWAYS_USED
C_DCACHE_ALWAYS_USED
C_D_AXI
C_USE_INTERRUPT
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Parameter
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Appendix A: Performance and Resource Utilization
Configuration Parameter Values
3 3
2 2
0 1
0 0
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 0
0 2
0 2
0 1
0 0
0 1
0 1
0 1
0 1
0 0
0 1
0 8
0 8
0 0
0 0
0 1
0 1
0 1
0 0
3 3 3 3
2 2 2 2
1 1 1 2
0 0 0 0
0 0 0 0
0 1 1 0
0 2 0 0
0 1 1 0
0 1 1 1
0 1 1 1
0 1 0 0
0 0 0 0
0 0 0 0
0 2 1 1
0 1 1 1
0 3 3 0
0 1 1 1
0 1 1 1
1 1 1 1
0 0 0 0
0 0 0 0
0 1 0 0
0 8 0 0
0 8 0 0
0 0 0 0
0 0 0 0
0 1 1 0
0 1 1 0
0 1 1 0
0 1 1 0
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