Xilinx MicroBlaze Reference Manual page 76

C_ICACHE_DATA_WIDTH
(128, 256 or 512 bits), or 512 bits.
When
C_FAULT_TOLERANT
a tag or instruction Block RAM.
The instruction cache issues burst accesses for the AXI4 interface when 32-bit data width is
used, otherwise single accesses are used.
Stream Buffers
When stream buffers are enabled, by setting the parameter
cache will speculatively fetch cache lines in advance in sequence following the last
requested address, until the stream buffer is full. The stream buffer can hold up to two
cache lines. Should the processor subsequently request instructions from a cache line
prefetched by the stream buffer, which occurs in linear code, they are immediately available.
The stream buffer often improves performance, since the processor generally has to spend
less time waiting for instructions to be fetched from memory.
C_ICACHE_DATA_WIDTH
each clock cycle, either 32 bits or an entire cache line.
To be able to use instruction cache stream buffers, area optimization must not be enabled.
Victim Cache
The victim cache is enabled by setting the parameter
defines the number of cache lines that can be stored in the victim cache. Whenever a cache
line is evicted from the cache, it is saved in the victim cache. By saving the most recent lines
they can be fetched much faster, should the processor request them, thereby improving
performance. If the victim cache is not used, all evicted cache lines must be read from
memory again when they are needed.
C_ICACHE_DATA_WIDTH
each clock cycle, either 32 bits or an entire cache line.
Note that to be able to use the victim cache, area optimization must not be enabled.
Instruction Cache Software Support
MSR Bit
The ICE bit in the MSR provides software control to enable and disable caches.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
determines the bus data width, either 32 bits, an entire cache line
is set to 1, a cache miss also occurs if a parity error is detected in
determines the amount of data transferred from the stream buffer
determines the amount of data transferred from/to the victim cache
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Chapter 2: MicroBlaze Architecture
C_ICACHE_STREAMS
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C_ICACHE_VICTIMS
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