Xilinx MicroBlaze Reference Manual page 58

Table 2-37: Page-Translation Bit Ranges by Page Size
Page SIZE
Size (TLBHI Field)
1 KB 000
4 KB 001
16 KB 010
64 KB
011
256 KB 100
1 MB 101
4 MB
110
16 MB
111
TLB Access
When the MMU translates a virtual address (the combination of PID and effective address)
into a physical address, it first examines the appropriate shadow TLB for the page
translation entry. If an entry is found, it is used to access physical memory. If an entry is not
found, the MMU examines the UTLB for the entry. A delay occurs each time the UTLB must
be accessed due to a shadow TLB miss. The miss latency ranges from 2-32 cycles. The DTLB
has priority over the ITLB if both simultaneously access the UTLB.
Figure 2-21, page 60
translation entry in one of the shadow TLBs or the UTLB. All valid entries in the TLB are
checked.
A TLB hit occurs when all of the following conditions are met by a TLB entry:
• The entry is valid
• The TAG field in the entry matches the effective address EPN under the control of the
SIZE field in the entry
• The TID field in the entry matches the PID
If any of the above conditions are not met, a TLB miss occurs. A TLB miss causes an
exception, described as follows:
A TID value of 0x00 causes the MMU to ignore the comparison between the TID and PID.
Only the TAG and EA[EPN] are compared. A TLB entry with TID=0x00 represents a process-
independent translation. Pages that are accessed globally by all processes should be
assigned a TID value of 0x00. A PID value of 0x00 does not identify a process that can access
any page. When PID=0x00, a page-translation hit only occurs when TID=0x00. It is possible
for software to load the TLB with multiple entries that match an EA[EPN] and PID
combination. However, this is considered a programming error and results in undefined
behavior.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Tag Comparison
Bit Range
TAG[0:21] - Address[0:21]
TAG[0:19] - Address[0:19]
TAG[0:17] - Address[0:17]
TAG[0:15] - Address[0:15]
TAG[0:13] - Address[0:13]
TAG[0:11] - Address[0:11]
TAG[0:9] - Address[0:9]
TAG[0:7] - Address[0:7]
shows the logical process the MMU follows when examining a page-
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Chapter 2: MicroBlaze Architecture
Physical Page
Page Offset
Number
Address[22:31] RPN[0:21]
Address[20:31] RPN[0:19]
Address[18:31] RPN[0:17]
Address[16:31] RPN[0:15]
Address[14:31] RPN[0:13]
Address[12:31] RPN[0:11]
Address[10:31] RPN[0:9]
Address[8:31] RPN[0:7]
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RPN Bits
Clear to 0
-
20:21
18:21
16:21
14:21
12:21
10:21
8:21
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