Xilinx MicroBlaze Reference Manual page 54

Each address shown in
page number represents the portion of the address translated by the MMU. The offset
represents the byte offset into a page and is not translated by the MMU. The virtual address
consists of an additional field, called the process ID (PID), which is taken from the PID
register (see Process-ID Register, page 33). The combination of PID and effective page
number (EPN) is referred to as the virtual page number (VPN). The value n is determined by
the page size, as shown in
System software maintains a page-translation table that contains entries used to translate
each virtual page into a physical page. The page size defined by a page translation entry
determines the size of the page number and offset fields. For example, when a 4 kB page
size is used, the page-number field is 20 bits and the offset field is 12 bits. The VPN in this
case is 28 bits.
Then the most frequently used page translations are stored in the translation look-aside
buffer (TLB). When translating a virtual address, the MMU examines the page-translation
entries for a matching VPN (PID and EPN). Rather than examining all entries in the table,
only entries contained in the processor TLB are examined. When a page-translation entry is
found with a matching VPN, the corresponding physical-page number is read from the
entry and combined with the offset to form the 32-bit physical address. This physical
address is used by the processor to reference memory.
System software can use the PID to uniquely identify software processes (tasks, subroutines,
threads) running on the processor. Independently compiled processes can operate in
effective-address regions that overlap each other. This overlap must be resolved by system
software if multitasking is supported. Assigning a PID to each process enables system
software to resolve the overlap by relocating each process into a unique region of virtual-
address space. The virtual-address space mappings enable independent translation of each
process into the physical-address space.
Page-Translation Table
The page-translation table is a software-defined and software-managed data structure
containing page translations. The requirement for software-managed page translation
represents an architectural trade-off targeted at embedded-system applications.
Embedded systems tend to have a tightly controlled operating environment and a well-
defined set of application software. That environment enables virtual-memory
management to be optimized for each embedded system in the following ways:
• The page-translation table can be organized to maximize page-table search
performance (also called table walking) so that a given page-translation entry is
located quickly. Most general-purpose processors implement either an indexed page
table (simple search method, large page-table size) or a hashed page table (complex
search method, small page-table size). With software table walking, any hybrid
organization can be employed that suits the particular embedded system. Both the
page-table size and access time can be optimized.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Figure 2-18 contains a page-number field and an offset field. The
Table 2-37.
www.xilinx.com
Chapter 2: MicroBlaze Architecture
Send Feedback
54