Xilinx MicroBlaze Reference Manual page 34

Table 2-19: Zone Protection Register (ZPR)
Bits Name
0:1 ZP0
2:3 ZP1
... ...
30:31 ZP15
Translation Look-Aside Buffer Low Register (TLBLO)
The Translation Look-Aside Buffer Low Register is used to access MMU Unified Translation
Look-Aside Buffer (UTLB) entries. It is controlled by the
MicroBlaze. The register is only implemented if
and
C_AREA_OPTIMIZED
instructions, the TLBLO is specified by setting Sa = 0x1003. When reading or writing TLBLO,
the UTLB entry indexed by the TLBX register is accessed. The register is readable according
to the memory management special registers parameter
The UTLB is reset on bit stream download (reset value is 0x00000000 for all TLBLO entries).
The UTLB is not reset by the external reset inputs: Reset and Debug_Rst. This means that
Note:
the entire UTLB must be initialized after reset, to avoid any stale data.
Figure 2-14 illustrates the TLBLO register and
values.
0
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Zone Protect
User mode (MSR[UM] = 1):
00 = Override V in TLB entry. No access to the page is allowed
01 = No override. Use V, WR and EX from TLB entry
10 = No override. Use V, WR and EX from TLB entry
11 = Override WR and EX in TLB entry. Access the page as writable
and executable
Privileged mode (MSR[UM] = 0):
00 = No override. Use V, WR and EX from TLB entry
01 = No override. Use V, WR and EX from TLB entry
10 = Override WR and EX in TLB entry. Access the page as writable
and executable
11 = Override WR and EX in TLB entry. Access the page as writable
and executable
Read/Write
is set to 0 (Performance). When accessed with the MFS and MTS
↑
RPN
Figure 2-14: TLBLO
www.xilinx.com
Chapter 2: MicroBlaze Architecture
Description
C_USE_MMU
is greater than 1 (User Mode),
C_USE_MMU
C_MMU_TLB_ACCESS
Table 2-20 provides bit descriptions and reset
22 23 24
↑ ↑
EX WR
Reset Value
0x00000000
configuration option on
.
28 29 30 31
↑ ↑ ↑ ↑ ↑
ZSEL W I M G
Send Feedback
34