Xilinx MicroBlaze Reference Manual page 231

lwi
Load Word Immediate
lwi
1 1 1 0 1 0
0 6
Description
Loads a word (32 bits) from the word aligned memory location that results from adding the
contents of register rA and the value IMM, sign-extended to 32 bits. The data is placed in register
rD. A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation
entry corresponding to the address is not found in the TLB.A data storage exception occurs if
access is prevented by a no-access-allowed zone protection. This only applies to accesses with user
mode and virtual protected mode enabled. An unaligned data access exception occurs if the two
least significant bits in the address are not zero.
Pseudocode
←
Addr (rA) + sext(IMM)
if TLB_Miss(Addr) and MSR[VM] = 1 then
←
ESR[EC]
MSR[UMS]
else if Access_Protected(Addr) and MSR[UM] = 1 and MSR[VM] = 1 then
ESR[EC]
MSR[UMS]
else if Addr[30:31]
ESR[EC]
else
←
(rD)
Registers Altered
• rD, unless an exception is generated, in which case the register is unchanged
• MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if a TLB miss exception or a data storage
exception is generated
• ESR[EC], ESR[S], if an exception is generated
• ESR[DIZ], if a data storage exception is generated
• ESR[W], ESR[Rx], if an unaligned data access exception is generated
Latency
• 1 cycle with
• 2 cycles with
Note
By default, Type B Instructions will take the 16-bit IMM field value and sign extend it to 32 bits to
use as the immediate operand. This behavior can be overridden by preceding the Type B
instruction with an imm instruction. See the instruction
immediate values.
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
rD, rA, IMM
rD rA
11
←
10010;ESR[S] 0
←
MSR[UM]; MSR[VMS]
← ←
10000;ESR[S] 0; ESR[DIZ]
←
MSR[UM]; MSR[VMS]
≠
0 then
← ←
00001; ESR[W] 1; ESR[S]
Mem(Addr)
=0
C_AREA_OPTIMIZED
C_AREA_OPTIMIZED
www.xilinx.com
Chapter 5: MicroBlaze Instruction Set Architecture
16
← ←
MSR[VM]; MSR[UM]
←
1
← ←
MSR[VM]; MSR[UM]
←
0; ESR[Rx]
=1
"imm," page 222
IMM
←
0; MSR[VM] 0
←
0; MSR[VM] 0
←
rD
for details on using 32-bit
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