Xilinx MicroBlaze Reference Manual page 99

Table 2-51: Trace Status Register (TSR)
Bits Name
17 Started
16 Overflow
15:0 Item Count
Trace Data Read Register
The Trace Data Read Register (TDRR) contains the oldest item read from the Embedded
Trace Buffer. When the register has been read, the next item is read from the trace buffer. It
is an error to read more items than are available in the trace buffer, as indicated by the item
count in the Trace Status Register. This register is a read-only register. Issuing a write request to
the register does nothing.
Since a trace data entity can consist of more than 18 bits, depending on the compression
level and stored data, the register may need to be read repeatedly to retrieve all
information for a particular data entity. This is detailed in
31
↑
Reserved
Table 2-52: Trace Data Read Register (TDRR)
Bits Name
17:0 Buffer Value
Table 2-53: Trace Counter Data Entities
Entity
Complete Trace
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Trace started, set to one when trace is started and cleared to zero
when it is stopped
Cycle count overflow, set to one when the cycle count overflows, and
cleared to zero by the Clear command
Sampled trace buffer item count
18 17
Figure 2-34: Trace Data Read Register
Embedded Trace Buffer item
Item Bits
1 17:3
2:0
2 17:6
5:1
0
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Chapter 2: MicroBlaze Architecture
Description
Table 2-53.
↑
Buffer Value
Description
Description
Cycle count for the executed instruction
Machine Status Register
Machine Status Register
Destination register address (r0 - r31), valid if written
Destination register written if set to one
Reset Value
0
0
0x0000
Reset Value
0x00000
[17:19]
[20:31]
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