Xilinx MicroBlaze Reference Manual page 23

Table 2-7: General Purpose Registers (R0-R31)
Bits Name
0:31 R0
0:31 R1 through R13
0:31 R14
0:31 R15
0:31 R16
0:31 R17
0:31 R18 through R31
Refer to Table 4-2
Special Purpose Registers
Program Counter (PC)
The Program Counter (PC) is the 32-bit address of the execution instruction. It can be read
with an MFS instruction, but it cannot be written with an MTS instruction. When used with
the MFS instruction the PC register is specified by setting Sa = 0x0000.
the PC and Table 2-8
0
Table 2-8: Program Counter (PC)
Bits Name
0:31 PC
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Always has a value of zero. Anything written to R0 is
discarded
32-bit general purpose registers
32-bit register used to store return addresses for
interrupts.
32-bit general purpose register. Recommended for storing
return addresses for user vectors.
32-bit register used to store return addresses for breaks.
If MicroBlaze is configured to support hardware
exceptions, this register is loaded with the address of the
instruction following the instruction causing the HW
exception, except for exceptions in delay slots that use BTR
instead (see "Branch Target Register
general purpose register.
R18 through R31 are 32-bit general purpose registers.
for software conventions on general purpose register usage.
provides a description and reset value.
Figure 2-3: PC
Program Counter
Address of executing instruction, that is, "mfs r2 0" stores the
address of the mfs instruction itself in R2.
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Chapter 2: MicroBlaze Architecture
Description
(BTR)"); if not, it is a
↑
PC
Description
Reset Value
0x00000000
-
-
-
-
-
-
Figure 2-3 illustrates
31
Reset Value
0x00000000
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