Xilinx MicroBlaze Reference Manual page 128

Table 3-1: Summary of MicroBlaze Core I/O (Cont'd)
Signal
M_AXI_IC_BREADY
M_AXI_IC_BUSER
M_AXI_IC_WACK
M_AXI_IC_ARID
M_AXI_IC_ARADDR
M_AXI_IC_ARLEN
M_AXI_IC_ARSIZE
M_AXI_IC_ARBURST
M_AXI_IC_ARLOCK
M_AXI_IC_ARCACHE
M_AXI_IC_ARPROT
M_AXI_IC_ARQOS
M_AXI_IC_ARVALID
M_AXI_IC_ARREADY
M_AXI_IC_ARUSER
M_AXI_IC_ARDOMAIN
M_AXI_IC_ARSNOOP
M_AXI_IC_ARBAR
M_AXI_IC_RID
M_AXI_IC_RDATA
M_AXI_IC_RRESP
M_AXI_IC_RLAST
M_AXI_IC_RVALID
M_AXI_IC_RREADY
M_AXI_IC_RUSER
M_AXI_IC_RACK
M_AXI_IC_ACVALID
M_AXI_IC_ACADDR
M_AXI_IC_ACSNOOP
M_AXI_IC_ACPROT
M_AXI_IC_ACREADY
M_AXI_IC_CRREADY
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Chapter 3: MicroBlaze Signal Interface Description
Interface I/O
Master Response ready
M_AXI_IC O
Slave Write response user signals
M_AXI_IC I
Slave Write acknowledge
M_ACE_IC O
Master Read address ID
M_AXI_IC O
Master Read address
M_AXI_IC O
Master Burst length
M_AXI_IC O
Master Burst size
M_AXI_IC O
Master Burst type
M_AXI_IC O
Master Lock type
M_AXI_IC O
Master Cache type
M_AXI_IC O
Master Protection type
M_AXI_IC O
Master Quality of Service
M_AXI_IC O
Master Read address valid
M_AXI_IC O
Slave Read address ready
M_AXI_IC I
Master Read address user signals
M_AXI_IC O
Master Read address domain
M_ACE_IC O
Master Read address snoop
M_ACE_IC O
Master Read address barrier
M_ACE_IC O
Slave Read ID tag
M_AXI_IC I
Slave Read data
M_AXI_IC I
Slave Read response
M_AXI_IC I
Slave Read last
M_AXI_IC I
Slave Read valid
M_AXI_IC I
Master Read ready
M_AXI_IC O
Slave Read user signals
M_AXI_IC I
Master Read acknowledge
M_ACE_IC O
Slave Snoop address valid
M_ACE_IC I
Slave Snoop address
M_ACE_IC I
Slave Snoop address snoop
M_ACE_IC I
Slave Snoop address protection type
M_ACE_IC I
Master Snoop ready
M_ACE_IC O
Slave Snoop response ready
M_ACE_IC I
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