Xilinx MicroBlaze Reference Manual page 132

Table 3-2: Effect of Reset Mode inputs
Reset_Mode[0:1]
00
01
10
11
Sleep and Pause Functionality
There are two distinct ways of halting MicroBlaze execution in a controlled manner:
• Software controlled by executing an MBAR instruction to enter sleep mode.
• Hardware controlled by setting the input signal Pause to pause the pipeline.
Software Controlled
When an MBAR instruction is executed to enter sleep mode and MicroBlaze has completed
all external accesses, the pipeline is halted and either the Sleep, Hibernate or Suspend
output signal is set. This indicates to external hardware that it is safe to perform actions
such as stopping the clock, resetting the processor or other IP cores. Different actions can
be performed depending on which output signal is set.
To wake up MicroBlaze when in sleep mode, one (or both) of the Wakeup input signals must
be set to one. In this case MicroBlaze continues execution after the MBAR instruction.
The Dbg_Wakeup output signal from MicroBlaze indicates that the debugger requests a
wake up. External hardware should handle this signal and wake up the processor, after
performing any other necessary hardware actions such as starting the clock.
If debug wake up is used, the software must be aware that this could be the reason for
waking up, and go to sleep again if no other action is required.
In the simplest case, where no additional actions are needed before waking up the
processor, one of the Wakeup inputs can be connected to the same signal as the MicroBlaze
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
MicroBlaze starts executing at the reset vector, defined by C_BASE_VECTORS. This
is the nominal default behavior.
MicroBlaze immediately enters sleep mode without performing any bus access,
just as if a SLEEP instruction had been executed. The Sleep output is set to 1.
When any of the Wakeup[0:1] signals is set, MicroBlaze starts executing at the
reset vector, defined by C_BASE_VECTORS.
This functionality can be useful in a multiprocessor configuration, allowing
secondary processors to be configured without LMB memory.
If C_DEBUG_ENABLED is 0, the behavior is the same as if Reset_Mode[0:1] = 00.
If C_DEBUG_ENABLED is greater than 0, MicroBlaze immediately enters debug halt
without performing any bus access, and the MB_Halted output is set to 1. When
execution is continued via the debug interface, MicroBlaze starts executing at the
reset vector, defined by C_BASE_VECTORS.
Reserved
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Chapter 3: MicroBlaze Signal Interface Description
Description
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