Core Interfaces And Register Space - Xilinx LogiCORE IP Video In to AXI4-Stream v1.0 Product Manual

Table 2-2: Virtex-7
Data Width
8
24
64
Table 2-3: Virtex-6
Data Width
8
24
64
Table 2-4: Kintex-7
Data Width
8
24
64
Table 2-5: Artix-7
Data Width
8
24
64
Table 2-6: Zynq-7000
Data Width
8
24
64

Core Interfaces and Register Space

Port Descriptions
The Video In to AXI4-Stream core uses industry standard control and data interfaces to
connect to other system components. The following sections describe the various interfaces
available with the core.
Video In to AXI4-Stream
PG043 April 24, 2012
FIFO Depth LUTs
32 83
1024 120
8192 221
FIFO Depth LUTs
32 79
1024 120
8192 209
FIFO Depth LUTs
32 79
1024 119
8192 208
FIFO Depth LUTs
32 80
1024 113
8192 208
FIFO Depth LUTs
32 74
1024 111
8192 209
Figure 2-1 illustrates an I/O diagram of the Video In to AXI4-Stream
www.xilinx.com
Core Interfaces and Register Space
FFs RAM 36/18
104 0/0
161 1/0
262 16/1
FFs RAM 36/18
104 0/0
161 1/0
262 16/1
FFs RAM 36/18
104 0/0
161 1/0
262 16/1
FFs RAM 36/18
104 0/0
161 1/0
262 16/1
FFs RAM 36/18
104 0/0
161 1/0
262 16/1
Product Specification
Fmax (MHz)
337
309
309
Fmax (MHz)
303
236
186
Fmax (MHz)
357
320
320
Fmax (MHz)
265
222
222
Fmax (MHz)
261
211
211
10