Xilinx MicroBlaze Reference Manual page 47

There are three cases where the branch prediction can cause a mispredict, namely:
• A conditional branch that should not have been taken, is actually taken,
• A conditional branch that should actually have been taken, is not taken,
• The target address of a return instruction is incorrect, which may occur when returning
from a function called from different places in the code.
All of these cases are detected and corrected when the branch or return instruction reaches
the execute stage, and the branch prediction bits or target address are updated in the BTC,
to reflect the actual instruction behavior. This correction incurs a penalty of 2 clock cycles.
The size of the BTC can be selected with
recommended setting uses one block RAM, and provides 512 entries. When selecting 64
entries or below, distributed RAM is used to implement the BTC, otherwise block RAM is
used.
When the BTC uses block RAM, and
by parity. In case of a parity error, the branch is not predicted. To avoid accumulating errors
in this case, the BTC should be cleared periodically by a synchronizing branch.
The Branch Target Cache is available when
C_AREA_OPTIMIZED
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
C_BRANCH_TARGET_CACHE_SIZE
C_FAULT_TOLERANT
is set to 0 (Performance).
www.xilinx.com
Chapter 2: MicroBlaze Architecture
is set to 1, block RAMs are protected
C_USE_BRANCH_TARGET_CACHE
. The default
is set to 1 and
47
Send Feedback