Microblaze Ethernet Ip Cores - Xilinx MIcroBlaze Development Spartan-3E 1600E Kit User Manual

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Table 14-1: FPGA Connections to the LAN83C185 Ethernet PHY (Continued)

MicroBlaze Ethernet IP Cores

The Ethernet PHY is primarily intended for use with MicroBlaze applications. As such, an
Ethernet MAC is part of the EDK Platform Studio's Base System Builder. Both the full
Ethernet MAC and the Lite version are available for evaluation, as shown in
The Ethernet Lite MAC controller core uses fewer FPGA resources and is ideal for
applications that do not require support for interrupts, back-to-back data transfers, and
statistics counters.
The Ethernet MAC core requires design constraints to meet the required performance.
Refer to the OPB Ethernet MAC data sheet (v1.02) for details. The OPB bus clock frequency
must be 65 MHz or higher for 100 Mbps Ethernet operations and 6.5 MHz or faster for
10 Mbps Ethernet operations.
MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide
UG257 (v1.1) December 5, 2007
FPGA Pin
Signal Name Number
E_RX_CLK V3
E_CRS U13
E_COL U6
E_MDC P9
E_MDIO U5
Figure 14-3: Ethernet MAC IP Cores for the Spartan-3E Starter Kit Board
Function
Receive Clock. 25 MHz in 100Base-TX mode, and 2.5 MHz in
10Base-T mode.
Carrier Sense
MII Collision Detect.
Management Clock. Serial management clock.
Management Data Input/Output.
MicroBlaze Ethernet IP Cores
Figure
UG257_14_03_060806
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