Xilinx MicroBlaze Reference Manual page 129

Table 3-1: Summary of MicroBlaze Core I/O (Cont'd)
Signal
M_AXI_IC_CRVALID
M_AXI_IC_CRRESP
M_AXI_IC_CDVALID
M_AXI_IC_CDREADY
M_AXI_IC_CDDATA
M_AXI_IC_CDLAST
Data_Addr[0:N-1]
Byte_Enable[0:3]
Data_Write[0:31]
D_AS
Read_Strobe
Write_Strobe
Data_Read[0:31]
DReady
DWait
DCE
DUE
Instr_Addr[0:31]
I_AS
IFetch
Instr[0:31]
IReady
IWait
ICE
IUE
Mn_AXIS_TLAST
Mn_AXIS_TDATA
Mn_AXIS_TVALID
Mn_AXIS_TREADY
MicroBlaze Processor Reference Guide
UG984 (v2016.2) June 8, 2016
UG984 (v2016.1) April 6, 2016
Chapter 3: MicroBlaze Signal Interface Description
Interface I/O
Master Snoop response valid
M_ACE_IC O
Master Snoop response
M_ACE_IC O
Master Snoop data valid
M_ACE_IC O
Slave Snoop data ready
M_ACE_IC I
Master Snoop data
M_ACE_IC O
Master Snoop data last
M_ACE_IC O
Data interface LMB address bus, N = 32 - 64
DLMB O
Data interface LMB byte enables
DLMB O
Data interface LMB write data bus
DLMB O
Data interface LMB address strobe
DLMB O
Data interface LMB read strobe
DLMB O
Data interface LMB write strobe
DLMB O
Data interface LMB read data bus
DLMB I
Data interface LMB data ready
DLMB I
Data interface LMB data wait
DLMB I
Data interface LMB correctable error
DLMB I
Data interface LMB uncorrectable error
DLMB I
Instruction interface LMB address bus
ILMB O
Instruction interface LMB address strobe
ILMB O
Instruction interface LMB instruction fetch
ILMB O
Instruction interface LMB read data bus
ILMB I
Instruction interface LMB data ready
ILMB I
Instruction interface LMB data wait
ILMB I
Instruction interface LMB correctable error
ILMB I
Instruction interface LMB uncorrectable error
ILMB I
Master interface output AXI4 channels
M0_AXIS.. O
M15_AXIS
write last
Master interface output AXI4 channels
M0_AXIS.. O
M15_AXIS
write data
Master interface output AXI4 channels
M0_AXIS.. O
M15_AXIS
write valid
Master interface input AXI4 channels
M0_AXIS.. I
M15_AXIS
write ready
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