Fujitsu F2MC-16LX MB90V580 Manuals

Table of Contents

• • 5

    Table of Contents

• 21

  Chapter 1 Overview

  • 21

    Features
  • 23

    Product Lineup
  • 23

    Table 1.2A MB90580 Series Product Lineup
  • 24

    Block Diagram

• 24

  Chapter 1 Overview

  • 24

    Figure 1.3A Block Diagram of MB90580 Series
  • 25

    Pin Assignment
    • 25

      SQFP-100 Pin Assignment
    • 25

      Figure 1.4A Pin Assignment of MB90580 (LQFP-100)
    • 26

      Pin Assignment
    • 26

      Figure 1.4B Pin Assignment of MB90580 (QFP-100)
  • 27

    Pin Functions
  • 27

    Table 1.5A Pin Functions (1/4) (STBC: with Standby Control)
  • 28

    Table 1.5B Pin Functions (2/4)
  • 29

    Table 1.5C Pin Functions (3/4)
  • 30

    Table 1.5D Pin Functions (4/4)
  • 31

    Table 1.5E I/O Circuit Format (1)
  • 32

    Table 1.5F I/O Circuit Format (2)
  • 33

    Table 1.5G I/O Circuit Format (3)
  • 34

    Figure 1.6A Using External Clock
  • 34

    Figure 1.6B Connection of Power Pins
  • 34

    Handling the Device

• 35

  Chapter 2 CPU

  • 35

    Cpu
    • 36

      Memory Space
    • 36

      Figure 2.1.1A Sample Relationship Between F2MC-16LX System and Memory Map
    • 37

      Figure 2.1.1B Sample Linear Addressing
    • 38

      Figure 2.1.1C Physical Addresses of Each Space
    • 38

      Table 2.1.1A Default Space
    • 39

      Figure 2.1.1D Sample Allocation of Multi-Byte Data in Memory
    • 39

      Figure 2.1.1E Execution of MOVW A, 080FFFFH
    • 40

      Registers
    • 40

      Figure 2.1.2A Special Registers
    • 41

      Figure 2.1.2B General-Purpose Registers
    • 41

      Figure 2.1.2C Program Counter
    • 42

      Figure 2.1.2D 32-Bit Data Transfer
    • 42

      Figure 2.1.2E AL-AH Transfer
    • 43

      Figure 2.1.2F Stack Manipulation Instruction and Stack Pointer
    • 44

      Figure 2.1.2G PS Structure
    • 44

      Figure 2.1.2H Condition Code Register Configuration
    • 45

      Figure 2.1.2I Register Bank Pointer
    • 45

      Figure 2.1.2J Interrupt Level Register

• 45

  Chapter 2 CPU

  • 45

    Table 2.1.2A Levels Indicated By the Interrupt Level Mask (ILM) Register
    • 46

      Table 2.1.2B Register Functions
    • 46

      Table 2.1.2C Relationship Between Registers
    • 47

      Figure 2.1.2K Generating a Physical Address in Direct Addressing Mode
    • 48

      Prefix Codes
    • 48

      Table 2.1.3A Bank Select Prefix
    • 49

      Figure 2.1.3A Interrupt Disable Instruction
    • 50

      Figure 2.1.3B Interrupt Disable Instructions and Prefix Codes
    • 50

      Figure 2.1.3C Consecutive Prefix Codes

• 51

  Chapter 3 Memory

  • 51

    Memory Access Modes
    • 51

      Table 3.1A Memory Access Mode
    • 52

      Mode Pins
    • 52

      Table 3.1.1A Mode Pins and Modes
    • 53

      Mode Data
    • 54

      Bus Mode
    • 54

      Figure 3.1.3A Access Areas and Physical Addresses in Each Bus Mode

• 55

  Chapter 3 Memory

  • 55

    Table 3.1.3A Sample Recommended Setting of Mode Pins and Mode Data
  • 55

    Table 3.1.3B Modes and Related External Pin Operations
  • 56

    External Memory Access
    • 56

      Block Diagram
    • 56

      Figure 3.2.1A External Bus Pin Control Circuit
    • 57

      Registers and Register Details
    • 59

      Table 3.2.0A Selecting the High-Order Address Bit Output Control
    • 62

      Operations
    • 62

      Figure 3.2.1A External Memory Access Timing Chart
    • 63

      Figure 3.2.1B External Memory Access Timing Chart
    • 64

      Figure 3.2.1C Ready Timing Chart
    • 65

      Figure 3.2.1D Hold Timing

• 67

  Chapter 4 Clock and Reset

  • 67

    Clock Generator
  • 67

    Figure 4.1A Clock Generator Circuit Block Diagram
  • 68

    Reset Causes
  • 68

    Table 4.2A Reset Causes
  • 69

    Figure 4.2A Reset Cause Bit Block Diagram
  • 69

    Figure 4.2B WDTC (Watch-Dog Timer Control Register)
  • 69

    Table 4.2B Reset Cause Bits
  • 70

    Operation After Reset Release
  • 70

    Figure 4.3A Source and Destination of Reset Vector and Mode Data

• 71

  Chapter 5 Watchdog Timer, Timebase Timer, and Watch Timer Functions

  • 71

    Outline
  • 72

    Block Diagram

• 72

  Chapter 5 Watchdog Timer, Timebase Timer, and Watch Timer Functions

  • 72

    Figure 5.2A Watchdog Timer, Timebase Timer, and Watch Timer Block Diagram
  • 73

    Registers and Register Details
    • 74

      WDTC (Watch-Dog Timer Control Register)
    • 74

      Table 5.3.1A Reset Cause Registers
    • 75

      Table 5.3.1B Watchdog Timer Interval Selection Bits
    • 76

      TBTC (Time Base Timer Control Register)
    • 76

      Table 5.3.2A Selecting the Time Base Timer Interval
    • 77

      Watch Timer Control Register (WTC)
    • 78

      Table 5.3.3A Watch Timer Interval Selection
  • 79

    Operation
    • 79

      Watch-Dog Timer
    • 79

      Figure 5.4.1A Watch-Dog Timer Operation
    • 80

      Time Base Timer
    • 80

      Watch Timer

• 81

  Chapter 6 Low Power Control Circuit

  • 81

    Outline
  • 82

    Block Diagram
  • 82

    Figure 6.2A Low-Power Consumption Control Circuit and Clock Generator

• 83

  Chapter 6 Low Power Control Circuit

  • 83

    Registers and Register Details
    • 83

      LPMCR (Low Power Mode Control Register)
  • 84

    Table 6.3.1A CG Bit Setting
  • 85

    CKSCR (Clock Selection Register)
  • 85

    Table 6.3.2A WS Bit Settings
  • 86

    Table 6.3.2B CS Bit Settings
  • 87

    Operations
    • 87

      Table 6.4A Low Power Consumption Mode Operating Statuses
    • 88

      Pseudo-Watch Mode
    • 88

      Sleep Mode
    • 89

      Stop Mode
    • 89

      Watch Mode
    • 90

      CPU Intermittent Operation Function
    • 90

      Hardware Standby Mode
    • 91

      Setting the Main Clock Oscillation Stabilization Waiting Period
    • 91

      Switching the Machine Clock
    • 92

      Figure 6.4.8A Clock Selection State Transition Diagram (1)
    • 93

      Figure 6.4.8B Clock Selection State Transition Diagram (2)
    • 93

      State Transition
    • 94

      Table 6.4.9A List of Transition Conditions

• 96

  Chapter 7 Interrupt

  • 97

    Figure 6.4.9A Low Power Consumption Mode Transition Diagram a
  • 98

    Figure 6.4.9B Low Power Consumption Mode Transition Diagram B
  • 99

    Figure 6.4.9C Low Power Consumption Mode Transition Diagram C
  • 100

    Figure 6.4.9D Low Power Consumption Mode Transition Diagram D

• 101

  Chapter 7 Interrupt

  • 101

    Outline
  • 102

    Causes of Interrupt
  • 102

    Table 7.2A Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers
  • 103

    Interrupt Vector
  • 103

    Table 7.3A MB90580 Interrupt Assignment Table (1/2)
  • 104

    Hardware Interrupt
    • 104

      Overview
    • 104

      Structure
    • 104

      Operation
    • 105

      Figure 7.4.3A Occurrence and Release of Hardware Interrupt
    • 106

      Figure 7.4.3B Hardware Interrupt Operation Flow
    • 106

      Table 7.4.3A Compensation Values for Interrupt Processing Cycle Count
    • 107

      Hardware Interrupt Ocurrence When Internal Resource Is Being Accessed
    • 107

      Interrupt Inhibit Instruction
    • 107

      Multiple Interrupts
    • 107

      Register Saving in Stack Upon Interrupt
    • 107

      Precaution in Using Hardware Interrupt
    • 107

      Figure 7.4.7A Registers Saved in Stack
  • 108

    Software Interrupt
    • 108

      Overview
    • 108

      Structure
    • 109

      Operation
    • 109

      Others
    • 109

      Figure 7.5.3A Occurrence and Release of Software Interrupt
  • 110

    Extended Intelligent I/O Service (EI2OS)
    • 110

      Overview
    • 110

      Figure 7.6.1A Outline of Extended Intelligent I/O Service
    • 111

      Structure
    • 112

      Table 7.6.2A ICS Bits, Channel Numbers, and Descriptor Addresses
    • 112

      Table 7.6.2B S Bits and End Conditions
    • 113

      Table 7.6.2C Interrupt Level Setting Bits and Interrupt Levels
    • 114

      Figure 7.6.2A Extended Intelligent I/O Service Descriptor Configuration
    • 117

      Operation
    • 117

      Figure 7.6.3A EI2OS Operation Flow
    • 118

      Figure 7.6.3B EI2OS Use Flow
    • 119

      EI2OS Execution Time
    • 119

      Table 7.6.4A Execution Time When the Extended I2OS Continues
    • 119

      Table 7.6.4B Data Transfer Compensation Values for Extended I2OS Execution Time
  • 120

    Exceptions
    • 120

      Exception Due to Execution of an Undefined Instruction

• 121

  Chapter 8 Parallel Ports

  • 121

    Outline
  • 122

    Block Diagram
  • 122

    Figure 8.2A Block Diagram of I/O Port
  • 122

    Figure 8.2B Block Diagram of Input Resistor Register
  • 122

    Figure 8.2C Block Diagram of Output Pin Register
  • 123

    Registers and Register Details
    • 123

      Figure 8.3A Registers of Parallel Ports
    • 124

      Port Data Register
    • 125

      Port Direction Registers
    • 126

      Input Resistor Register
    • 126

      Output Pin Register
    • 127

      Analogue Input Enable Register
    • 127

      Low Noise Output Select Register

• 129

  Chapter 9 Dtp/External Interrupt

  • 129

    Outline
  • 129

    Block Diagram
  • 129

    Figure 9.2A Block Diagram of Dtp/External Interrupt
  • 130

    Registers and Register Details
    • 130

      Interrupt/Dtp Enable Register (ENIR: Enable Interrupt Request Register)
    • 131

      Interrupt/Dtp Cause Register (EIRR: External Interrupt Request Register)
    • 131

      Request Level Setting Register (ELVR: External Level Register)
  • 132

    Operations
    • 132

      External Interrupts
    • 132

      Figure 9.4.1A External Interrupt
    • 133

      DTP Operation
    • 133

      Figure 9.4.2A Timing to Cancel the External Interrupt at the End of DTP Operation
    • 133

      Figure 9.4.2B Sample Interface to the External Peripheral
    • 134

      Switching Between External Interrupt and DTP Requests
    • 134

      Figure 9.4.3A Switching Between External Interrupt and DTP Requests
  • 135

    Notes On Use
    • 135

      Conditions On the Externally Connected Peripheral When DTP Is Used
    • 135

      Recovery From Standby
    • 135

      External Interrupt/Dtp Operation Procedure
    • 135

      External Interrupt Request Level
    • 135

      Figure 9.5.4A Clearing the Cause Hold Circuit Upon Level Set

• 137

  Chapter 10 Delayed Interrupt Generation Module

  • 137

    Outline
  • 137

    Block Diagram
  • 137

    Registers and Register Details
  • 137

    Figure 10.2A Block Diagram of Delayed Interrupt Generation Module
  • 138

    Operations
    • 138

      Delayed Interrupt Occurrence
  • 138

    Notes On Operation
    • 138

      Delayed Interrupt Request Lock
    • 138

      Figure 10.4.1A Delayed Interrupt Issuance

• 139

  Chapter 11 Communication Prescaler

  • 139

    Outline
  • 139

    Block Diagram
  • 139

    Figure 11.2A Block Diagram of Communication Prescaler
  • 140

    Register and Register Details
    • 140

      Clock Division Control Registers
  • 141

    Operations

• 143

  Chapter 12 UART

  • 143

    Outline
  • 144

    Block Diagram
  • 144

    Figure 12.2A Block Diagram of UART
  • 145

    Register and Register Details
    • 145

      Figure 12.3A Registers of UART
    • 146

      Serial Mode Register (SMR0/1/2/3/4)
    • 148

      Serial Control Register (SCR0/1/2/3/4)
    • 150

      Serial Input Data Register (SIDR0/1/2/3/4)/ Serial Ouput Data Register (SODR0/1/2/3/4)
    • 150

      Serial Status Register (SSR0/1/2/3/4)
  • 152

    Operations
    • 152

      Operation Modes
    • 152

      UART Clock Selection
    • 152

      Table 12.4.1A UART Operation Modes
    • 152

      Table 12.4.2A Baud Rate (F Indicates the Machine Clock.)
    • 153

      Table 12.4.2B Baud Rates and Reload Values
    • 154

      Asynchronous Mode
    • 154

      Figure 12.4.3A Transfer Data Format (Modes 0 and 1)
    • 155

      CLK Synchronous Mode
    • 155

      Figure 12.4.4A Transfer Data Format (Mode 2)
    • 157

      Interrupt Occurrence and Flag Set Timing
    • 157

      Figure 12.4.5A Timing to Set PE, ORE, FRE, and RDRF (Mode 0)
    • 157

      Figure 12.4.5B Timing to Set ORE, FRE, and RDRF (Mode 1)
    • 158

      Figure 12.4.5C Timing to Set ORE and RDRF (Mode 2)
    • 158

      Figure 12.4.5D Timing to Set TDRE (Modes 0 and 1)
    • 158

      Figure 12.4.5E Timing to Set TDRE (Mode 2)
    • 159

      I2OS (Intelligent I/O Service)
    • 159

      Notes On Use
    • 159

      Application
    • 159

      Figure 12.4.8A Sample System Configuration in Mode 1
    • 160

      Figure 12.4.8B Flow Chart of Communication in Mode 1

• 161

  Chapter 13 IE Bus

  • 161

    Outline
  • 162

    Block Diagram
  • 162

    Figure 13.2A Block Diagram of IE Bus
  • 163

    Registers and Register Details
    • 163

      Figure 13.3A Registers of IE BUS (1/3)
    • 164

      Figure 13.3B Registers of IE BUS (2/3)
    • 165

      Figure 13.3C Registers of IE BUS (3/3)
    • 166

      Command Register Upper Byte (CMRH)
    • 166

      Table 13.3.1A Transmission Mode
    • 167

      Table 13.3.1B Setting for GOTM and GOTS
    • 168

      Command Register Lower Byte (CMRL)
    • 168

      Table 13.3.2A Interval for the Occurrence of Data Transmit Interrupt
    • 168

      Table 13.3.2B Interval for the Occurrence of Data Transmit Interrupt
    • 168

      Table 13.3.2C Interval for the Occurrence of Data Transmit Interrupt
    • 169

      Table 13.3.2D Internal Clock Frequency
    • 170

      Slave Address Register (SAWH, SAWL)
    • 170

      Unit Address Register (MAWH, MAWL)
    • 171

      Mutliaddress, Control Bit Set Register (DCWR)
    • 171

      Table 13.3.5A Control Bits Setting
    • 172

      Table 13.3.6A Number of Transmit Data Bytes Setting
    • 172

      Telegraph Length Set Register (DEWR)
    • 173

      Status Register Upper Byte (STRH)
    • 175

      Status Register Lower Byte (STRL)
    • 176

      Table 13.3.8A Status Flag
    • 177

      Lock Read Register (LRRH, LRRL)
    • 178

      Master Address Read Register (MARH, MARL)
    • 179

      Multiaddress, Control Bit Read Register (DCRR)
    • 180

      Telegraph Length Read Register (DERR)
    • 181

      Read Data Buffer (RDB)
    • 181

      Table 13.3.13A Time Required for Next Data Receive After Receive Buffer Full Interrupt Occurred
    • 182

      Table 13.3.14A Data Write Time After WDB Empty Interrupt
    • 182

      Write Data Buffer (WDB)
  • 183

    Iebus Communication Protocol
    • 183

      Overview
    • 183

      Table 13.4.1A Iebus Transfer Rates
    • 184

      Determining Bus Mastership (Arbitration)
    • 184

      Communication Mode
    • 184

      Table 13.4.3A Transfer Rate and Maximum Number of Transfer Byte in Each Communication Mode
    • 185

      Communication Address
    • 185

      Multiaddress Communication
    • 186

      Transfer Protocol
    • 187

      Table 13.4.6A Number of Transmit Data Bytes Setting
    • 190

      Transmit Data
    • 190

      Table 13.4.7A Control Bits Setting
    • 190

      Table 13.4.7B the Control Command That Can Be Executed By a Locked Slave Unit
    • 191

      Table 13.4.7C Meaning of Slave Status
    • 193

      Bit Format
  • 194

    Operation
    • 194

      Iebus Control
    • 195

      Table 13.5.1A Time Required to Write Transmit Data to WDB After Transmit Interrupt Has Occurred
    • 197

      Communication Status
    • 197

      Table 13.5.2A Meaning of Status Code ST3-0 for Master, Slave Transmit
    • 197

      Table 13.5.2B Meaning of Status Code ST3-0 for Master Receive
    • 198

      Table 13.5.2C Meaning of Status Code ST3-0 for Slave Receive
    • 198

      Table 13.5.2D Meaning of Status Code ST3-0 for Multiaddress Receive
    • 199

      Program Flow Example for Iebus Controller
    • 206

      Timing Diagram of Multiple Frame Transmission
    • 206

      Figure 13.5.4A When Setting '1' On WDBC (Master Side of Master Transmission)
    • 207

      Figure 13.5.4B When Setting '0' On WDBC (Master Side of Master Transmission)
    • 208

      Timing Diaram of Transmission Data When an Error Is Generated
    • 208

      Figure 13.5.5A Error Happened On the Slave Side When Master Transmission
    • 209

      Figure 13.5.5B Error Happened On the Master Side When Master Transmission

• 211

  Chapter 14 8/16-Bit PPG

  • 211

    Outline
  • 212

    Block Diagram
  • 212

    Figure 14.2A 8-Bit PPG Ch0 Block Diagram
  • 213

    Figure 14.2B 8-Bit PPG Ch1 Block Diagram
  • 214

    Registers and Register Details
    • 214

      Figure 14.3A Registers of 8/16-Bit PPG
    • 215

      PPG0 Operation Mode Control Register (PPGC0)
    • 217

      PPG1 Operation Mode Control Register (PPGC1)
    • 219

      PPG0, 1 Output Pin Control Register (PPGOE)
    • 220

      Reload Register (PRLL/PRLH )
  • 221

    Operations
  • 221

    Table 14.4A Reload Operation and Pulse Output
  • 222

    Figure 14.4A PPG Output Operation, Output Waveform
  • 223

    Figure 14.4B 8+8 PPG Output Operation Waveform
  • 225

    Figure 14.4C Write Timing Chart
  • 225

    Figure 14.4D PRL Write Operation Block Diagram

• 227

  Chapter 15 16-Bit Reload Timer (With Event Count Function)

  • 227

    Outline
  • 228

    Block Diagram
  • 228

    Figure 15.2A Block Diagram of 16-Bit Reload Timer
  • 229

    Registers and Register Details
    • 229

      Figure 15.3A Registers of 16-Bit Reload Timer
    • 230

      Figure 15.3.1A Timer Control Status Register
    • 230

      Timer Control Status Register (TMCSR)
    • 233

      Figure 15.3.2A 16-Bit Timer Register and 16-Bit Reload Register
    • 233

      TMR (16-Bit Timer Register)/Tmrlr (16-Bit Reload Register)
  • 234

    Operation
    • 234

      Internal Clock Operation
    • 234

      Figure 15.4.1A Counter Activation and Operation
    • 235

      Underflow Operation
    • 235

      Figure 15.4.2A Underflow Operation
    • 236

      Input Pin Functions (For Internal Clock Mode)
    • 236

      External Event Counter
    • 236

      Figure 15.4.3A Trigger Input Operation
    • 236

      Figure 15.4.3B Gate Input Operation
    • 237

      Output Pin Functions
    • 237

      Intelligent I/O Service (I2OS) Function and Interrupts
    • 237

      Figure 15.4.5A Output Pin Functions (1)
    • 237

      Figure 15.4.5B Output Pin Functions (2)
    • 238

      Counter Operation State
    • 238

      Figure 15.4.7A Counter State Transitions

• 239

  Chapter 16 A/D Converter

  • 239

    Outline
  • 240

    Block Diagram
  • 240

    Figure 16.2A Block Diagram of A/D Converter
  • 241

    Registers and Register Details
    • 241

      Figure 16.3A Registers of A/D Converter
    • 242

      Control Status Registers (ADCS1 and ADCS2)
    • 242

      Figure 16.3.1A Control Status Registers
    • 246

      ADCR1 and ADCR0 (Data Registers)
    • 246

      Figure 16.3.2A Data Registers
  • 248

    Operations
  • 249

    Figure 16.4A Flow Chart of A/D Conversion
  • 253

    Figure 16.4B Flow Chart of Data Protection Function
  • 254

    Notes On Use
    • 254

      Other Considerations

• 255

  Chapter 17 D/A Converter

  • 255

    Outline
  • 256

    Block Diagram
  • 256

    Figure 17.2A Block Diagram of D/A Cobverter
  • 257

    Registers and Register Details
    • 257

      Figure 17.3A Register of D/A Converter
    • 258

      DACR0/1 ( D/A Control Register)
    • 258

      DAT0/1 ( D/A Data Register)
  • 259

    Operations
  • 259

    Table 17.4A Theoretical Values of D/A Converter Output Voltages

• 261

  Chapter 18 Pulse Width Counter (PWC) Timer

  • 261

    Outline
  • 262

    Block Diagram
  • 262

    Figure 18.2A Lock Diagram of Pulse Width Counter Timer
  • 263

    Regiaters and Register Details
    • 263

      Figure 18.3A Register of Pulse Width Counter Timer
    • 264

      PWC Control Status Register (PWCSR)
    • 269

      PWC Data Buffer Register (PWCR)
    • 270

      Divide Ratio Control Register (DIVR)
    • 271

      PWC Noise Cancelling Register (RNCR)
  • 272

    Operations
  • 272

    Figure 18.4A Timer Operation (Single-Shot Mode)
  • 272

    Figure 18.4B Timer Operation (Reload Mode)
  • 273

    Figure 18.4C Pulse Width Count Operation (Single-Shot Count Mode, "H" Width Count Mode)
  • 273

    Figure 18.4D Pulse Width Count Operation (Continuous Count Mode, "H" Width Count Mode)
  • 274

    Table 18.4A Count Clock Selection
  • 275

    Figure 18.4E Operation Mode Selection
  • 276

    Table 18.4B Start and Stop Bit Functions
  • 276

    Table 18.4C Operating State Indicator Bit Functions
  • 278

    Table 18.4D Count Clock and Period
  • 279

    Figure 18.4F Flowchart of Timer Mode Operation
  • 280

    Table 18.4E Count Input Pin Selection (N = 3 to 0)
  • 281

    Table 18.4F Count Modes
  • 283

    Table 18.4G Pulse Width Count Range
  • 284

    Figure 18.4G Flowchart of Operation in Pulse Width Count Mode
  • 285

    Precautions

• 287

  Chapter 19 Clock Monitor Function

  • 287

    Outline
  • 287

    Block Diagram
  • 287

    Figure 19.2A Block Diagram of Clock Monitor Function
  • 288

    Registers and Register Details
    • 288

      Clock Output Enable Register (CLKR)
    • 288

      Figure 19.3A Registers of Clock Monitor Function

• 289

  Chapter 20 16-Bit I/O Timer

  • 289

    Outline
  • 291

    Block Diagram
    • 291

      Overall Block Diagram of 16-Bit I/O Timer
    • 291

      Figure 20.2.1A Overall Block Diagram of 16-Bit I/O Timer
    • 292

      Block Diagram of 16-Bit Free-Run Timer
    • 292

      Block Diagram of Output Comparison
    • 292

      Figure 20.2.2A Block Diagram of 16-Bit Free-Run Timer
    • 292

      Figure 20.2.3A Block Diagram of Output Comparison
    • 293

      Block Diagram of Input Capture
    • 293

      Figure 20.2.4A Block Diagram of Input Capture
  • 294

    Registers and Register Details
    • 294

      16-Bit Free-Run Timer
    • 294

      Figure 20.3.1A Registers of 16-Bit Free-Run Timer
    • 298

      Output Comparison
    • 298

      Figure 20.3.2A Registers of Output Comparsion
    • 302

      Input Capture
    • 302

      Figure 20.3.3A Register of Input Capture
  • 305

    Operations
    • 305

      16-Bit Free-Run Timer
    • 306

      16-Bit Output Compare
    • 307

      16-Bit Input Capture
  • 308

    Timing
    • 308

      16-Bit Free-Run Timer Count Timing
    • 309

      Output Compare Timing
    • 310

      Input Capture Input Timing

• 311

  Chapter 21 ROM Correction Module

  • 311

    Outline
  • 311

    Block Diagram
  • 311

    Figure 21.2A Block Diagram of ROM Correction Module
  • 312

    Registers and Register Details
    • 312

      Program Address Detect Register 0/1 (PADR0/PADR1)
    • 312

      Figure 21.3A Registers of ROM Correction Module
    • 313

      Program Address Detect Control Status Register (PACSR)
  • 314

    Operations
  • 315

    Application Example
  • 315

    Figure 21.5A System Structure Example
  • 316

    Figure 21.5B ROM Correction Processing Example
  • 317

    Figure 21.5C ROM Correction Processing Flow Diagram

• 319

  Chapter 22 ROM Mirroring Module

  • 319

    Outline
  • 319

    Block Diagram
  • 319

    Figure 22.2A Block Diagram of ROM Mirroring Module
  • 320

    Registers and Register Details
    • 320

      ROM Mirror Function Select Register
    • 320

      Figure 22.3A Register of ROM Mirroring Module
    • 321

      Figure 22.3B Memory in Single Chip Mode
    • 321

      Figure 22.3C Memory in Internal ROM External Bus Mode

• 323

  Appendix A I/O Map

  • 323

    I/O Map
  • 323

    Table A.1A I/O Map

• 329

  Appendix B Instructions

  • 329

    Addressing
    • 329

      Effective Address Field
    • 329

      Table B.1.1A Effective Address Field
    • 330

      Addressing Details
  • 332

    Fig. B.1.2A Register List Configuration
  • 334

    Instruction Set
    • 334

      Table B.2A Explanation of Items in Table of Instructions
    • 336

      Table B.2B Explanation of Symbols in Table of Instructions
    • 337

      Table B.2C Effective Address Fields
    • 338

      Table B.2D Number of Execution Cycles for Each Form of Addressing
    • 338

      Table B.2E Compensation Values for Number of Cycles Used to Calculate Number of Actual Cycles
    • 339

      Table B.2F Compensation Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles
    • 340

      F 2 MC-16LX Instruction Set (351 Instructions)
    • 340

      Table B.2.1A Transfer Instructions (Byte) (41 Instructions)
    • 341

      Table B.2.1B Transfer Instructions (Word/Long-Word) (38 Instructions)
    • 342

      Table B.2.1C Addition and Subtraction Instructions (Byte/Word/Long-Word) (42 Instructions)
    • 343

      Table B.2.1D Increment and Decrement Instructions (Byte/Word/Long-Word) (12 Instructions)
    • 343

      Table B.2.1E Compare Instructions (Byte/Word/Long-Word) (11 Instructions)
    • 344

      Table B.2.1F Unsigned Multiplication and Division Instructions (Word/Long-Word) (11 Instructions)
    • 345

      Table B.2.1G Signed Multiplication and Division Instructions (Word/Long-Word) (11 Instructions)
    • 346

      Table B.2.1H Logical 1 Instructions (Byte/Word) (39 Instructions)
    • 347

      Table B.2.1I Logical 2 Instructions (Long-Word) (6 Instructions)
    • 347

      Table B.2.1J Sign Inversion Instructions (Byte/Word) (6 Instructions)
    • 347

      Table B.2.1K Normalize Instruction (Long-Word) (1 Instruction)
    • 348

      Table B.2.1L Shift Instructions (Byte/Word/Long-Word) (18 Instructions)
    • 349

      Table B.2.1M Branch 1 Instructions (31 Instructions)
    • 350

      Table B.2.1N Branch 2 Instructions (19 Instructions)
    • 351

      Table B.2.1O Other Control Instructions (Byte/Word/Long-Word) (36 Instructions)
    • 352

      Table B.2.1P Bit Manipulation Instructions (22 Instructions)
    • 353

      Table B.2.1Q Accumulator Manipulation Instructions (Byte/Word) (6 Instructions)
    • 353

      Table B.2.1R String Instructions (10 Instructions)
  • 354

    Instruction Map
    • 354

      Basic Page Map
  • 354

    Fig. B.3A Structure of F 2 MC-16LX Instruction Map
  • 355

    Fig. B.3B Correspondence Between Actual Instructions and the Instruction Maps
  • 356

    Table B.3.1A Basic
  • 357

    Table B.3.1B Bit Manipulation Instruction Map (First Byte = 6 CH)
  • 358

    Table B.3.1C Character String Manipulation Instruction Map (First Byte = 6EH)
  • 359

    Table B.3.1D Two-Byte Instruction Map (First Byte = 6FH)
  • 360

    Table B.3.1E "Ea" Instructions 1 (First Byte = 70H)
  • 361

    Table B.3.1F "Ea" Instructions 22 (First Byte = 71H)
  • 362

    Table B.3.1G "Ea" Instructions 3 (First Byte = 72H)
  • 363

    Table B.3.1H "Ea" Instructions 4 (First Byte = 73H)
  • 364

    Table B.3.1I "Ea" Instructions 5 (First Byte = 74H)
  • 365

    Table B.3.1J "Ea" Instructions 6 (First Byte = 75H)
  • 366

    Table B.3.1K "Ea" Instructions 7 (First Byte = 76H)
  • 367

    Table B.3.1L "Ea" Instructions 8 (First Byte = 77H)
  • 368

    Table B.3.1M "Ea" Instructions 9 (First Byte = 78H)
  • 369

    Table B.3.1N MOVEA Rwi, Ea (First Byte = 79H)
  • 370

    Table B.3.1O MOV Ri, Ea (First Byte = 7AH)
  • 371

    Table B.3.1P MOVW Rwi, Ea (First Byte = 7BH)
  • 372

    Table B.3.1Q MOV Ea, Ri (First Byte = 7CH)
  • 373

    Table B.3.1R MOVW Ea, Rwi (First Byte = 7DH)
  • 374

    Table B.3.1S CH Ri, Ea (First Byte = 7EH)
  • 375

    Table B.3.1T XCHW Rwi, Ea (First Byte = 7FH)

• 377

  Appendix C the Flash Memory in the MB90F583

  • 377

    Outline
  • 378

    Sector Structure of 1M Bit Flash Memory
  • 378

    Figure C.2A Sector Structure of 1M Bit Flash Memory
  • 379

    Flash Control Register (FMCS)
  • 380

    Figure C.3A Timing of RDYINT and RDY
  • 381

    Automatic Algorithm Initiation Method
  • 381

    Table C.4A Command Sequence Definitions
  • 382

    Automatic Algorithm Execution Status
    • 382

      Table C.5A Hardware Sequence Flag's Bit Assignment
    • 382

      Table C.5B Hardware Sequence Flag
    • 383

      Data Polling Flag (DQ7)
    • 383

      Table C.5.1A Status Change of Data Polling Flag (DQ7)
    • 384

      Table C.5.2A Status Change of Toggle Bit Flag (DQ6)
    • 384

      Toggle Bit Flag (DQ6)
    • 385

      Exceeded Timing Limits Flag (DQ5)
    • 385

      Table C.5.3A Status Change of Exceeded Timing Limits Flag (DQ5)
    • 386

      Sector Erase Timer Flag (DQ3)
    • 386

      Table C.5.4A Status Change of Sector Erase Tomer Flag (DQ3)
  • 387

    Notes On Flash Memory Program/Erase
    • 387

      Read/Reset Status
    • 388

      Data Programming
    • 389

      Figure C.6.2A Example Flowchart of Progamming the Flash Memory
    • 390

      Chip Erase
    • 390

      Sector Erase
    • 391

      Figure C.6.4A Example Flowchart of Erasing Flash Memory
    • 392

      Suspend Sector Erase
    • 392

      Resume Sector Erase