Generation Of Transmit Interrupt And Timing Of Flag Set; Fig. 12.10 Transmission And Timing Of Flag Set - Fujitsu MB90420/5 (A) Series Hardware Manual

12.5.2 Generation of Transmit Interrupt and Timing of Flag Set

At transmission, the interrupt is generated in the state which the next data can be written to the output data
register (SODR0/1).
n Generation of transmit interrupt and timing of flag set
The transmit data empty flag bit (SSR0/1: TDRE) is set to 1 when data written to the output data register
(SODR0/1) is transferred to the transmit shift register and in the state which the next data can be written.
When transmit data is written to SODR0/1, TDRE is cleared to 0. Figure 12.10 shows the transmission and
the timing of the flag set.
[Operation modes 0 and 1]
Writing to SODR
TDRE
Output to SOT0/1
[Operation mode 2]
Writing to SODR
TDRE
Output to SOT0/1
ST : Start bit
D0 to D7 : Data bits
SP : Stop bit
A/D : Address/data select bit
• Timing of transmit interrupt generation
Immediately after the TDRF flag is set to 1 when the transmit interrupt is enabled (SSR0/1: TIE = 1), a
transmit interrupt request (#38, #40) is issued.
Note: Since the TDRE is 1 in the initial state, when the transmit interrupt is enabled (TIE = 1), a transmit
completion interrupt is generated immediately. The TDRE is a read-only bit and can only be cleared
when new data is written to the output data register (SODR0/1). Take care for timing of the transmit
interrupt enable.
Generation of
transmit interrupt
ST
D0 D1 D2 D3 D4 D5 D6 D7
Generation of
transmit interrupt
D0 D1 D2 D3 D4 D5 D6 D7

Fig. 12.10 Transmission and Timing of Flag Set

UART
Generation of transmit
interrupt
D0 D1 D2 D3 D4 D5 D6
12-21
Generation of
transmit interrupt
SP
ST
A/D SP D0 D1 D2
D3
D7