Bus Control Register (Ibcr) - Fujitsu F2MC-16LX Hardware Manual

22.2.2 Bus Control Register (IBCR)

This section describes the configuration and functions of the bus control register
(IBCR).
I Bus control register (IBCR)
The diagram below shows the bit configuration of the bus control register (IBCR).
Bus control register
Address: 000089
The functions of bits in the bus control register (IBCR) are as follows.
[Bit 15] BER: Bus ERror
This bit is a bus error interrupt request flag. The function of this flag in write and read
operations is different.
(During writing)
0
1
(During reading)
0
1
If this bit is set, the EN bit of the ICCR register is cleared and the I
stop state with the data transfer interrupted.
[Bit 14] BEIE: Bus Error Interrupt Enable
This bit is used to enable bus error interrupts.
0
1
If, with this bit set to "1", the BER bit is set to "1", an interrupt is generated.
15 14
H
BER BEIE SCC MSS ACK GCAA INTE INT
Read/write
(R/W)(R/W)(R/W)(R/W)(R/W)(R/W) (R/W)(R/W)
Initial value
(0) (0)
Bus error interrupt request flag is cleared.
Not applicable
No bus error was detected.
An illegal start or stop condition was detected in data transfer mode.
Bus error interrupts prohibited
Bus error interrupts allowed
13 12 11 10 9
(0) (0) (0) (0) (0)
2
CHAPTER 22 I C INTERFACE
8 Bit number
IBCR
(0)
2
C interface enters the
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