Processor Status (Ps) - Fujitsu MB90335 Series Hardware Manual

MB90335 Series
2.6.3

Processor Status (PS)

The processor status (PS) register consists of the bits controlling the CPU operation
and the bits indicating the CPU status.
■ Processor Status (PS)
As shown in Figure 2.6-6, the upper bytes of the PS register consist of the register bank pointers (RP) and
the interrupt level mask register (ILM) that indicate the starting address of a register bank. The lower bytes
of the PS register consist of the condition code register (CCR), containing the flags to be set or reset
depending on the results of instruction execution or interrupt occurrences.
bit
PS
■ Condition Code Register (CCR)
Figure 2.6-7 shows the structure of the condition code register.
bit 7
-
Initial value -
●
Interrupt enable flag (I)
Interrupts other than software interrupts are enabled when the I flag is "1," and are disabled when the I flag
is "0". The I flag is cleared to "0" by a reset.
●
Stack flag (S)
When the S flag is "0", USP is enabled as the stack manipulation pointer. When the S flag is "1", SSP is
enabled as the stack manipulation pointer. The S flag is set to "1" by an interrupt reception or a reset.
●
Sticky bit flag (T)
"1" is set in the T flag when there is one or more "1" in the data shifted out from the carry after execution of
a logical right/arithmetic right shift instruction. Otherwise, "0" is set in the T flag.
●
Negative flag (N)
The "1" is set in the N flag when the MSB of the operation result is "1". Otherwise, N flag is cleared to "0".
CM44-10137-6E
Figure 2.6-6 Processor Status (PS) Structure
15 13 12
ILM
Figure 2.6-7 Structure of Condition Code Register (CCR)
6 5 4
I S T
0 1 *
FUJITSU MICROELECTRONICS LIMITED
8 7
RP
3 2 1
N Z V
* * *
CHAPTER 2 CPU
2.6 Registers
0
CCR
0
C : CCR
* * : Undefined value
33