Dma Descriptor - Fujitsu F2MC-16LX Hardware Manual

3.6.1

DMA Descriptor

The DMA descriptor is located in internal RAM within a range from "000100
"00017F " consisting of 8 bytes x 16 channels.
H
I DMA descriptor configuration
A DMA descriptor consists of 8 bytes x 16 channels.
configuration shown in the Figure 3.6-2 "Configuration of µDMA descriptor".
"Relationship between channel number and descriptor address" lists the relationship between
channel number and DMA descriptor address.
Descriptor
header address
Table 3.6-1 Relationship between channel number and descriptor address
DMA enable
register
EN0
EN1
EN2
EN3
EN4
EN5
EN6
EN7
EN8
EN9
Figure 3.6-2 Configuration of µ µ µ µ DMA descriptor
MSB
Upper 8 bits of data counter (DCTH)
Lower 8 bits of data counter (DCTL)
Upper 8 bits of I/O register address pointer (IOAH)
Lower 8 bits of I/O register address pointer (IOAL)
DMA control register (DMACS)
Upper 8 bits of buffer address pointer (BAPH)
Middle 8 bits of buffer address pointer (BAPM)
Lower 8 bits of buffer address pointer (BAPL)
Descriptor
Channel
address
0 000100
1 000108
2 000110
3 000118
4 000120
5 000128
6 000130
7 000138
8 000140
9 000148
Each DMA descriptor has the
Resource interrupt request
INT0
H
PWC0
H
PPG0/PPG1 counter borrow
H
PPG2/PPG3 counter borrow
H
PPG4/PPG5 counter borrow
H
Input capture (channel 0) read
H
Input capture (channel 1) read
H
UART receive completed
H
Output compare (channel 0) match
H
Output compare (channel 1) match
H
CHAPTER 3 INTERRUPT
" to
H
Table 3.6-1
LSB
H
L
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