ABB Relion 650 Series Technical Manual page 365

1MRK 506 326-UUS B
11.5.6 Operation principle
11.5.6.1 Directional comparison logic function
The directional comparison function contains logic for blocking overreaching and permissive
overreaching schemes.
The circuits for the permissive overreaching scheme contain logic for current reversal and weak-
end infeed functions. These functions are not required for the blocking overreaching scheme.
Use the independent or inverse time functions in the directional ground-fault protection module
to get back-up tripping in case the communication equipment malfunctions and prevents
operation of the directional comparison logic.
Figure 193
11.5.6.2 Fault current reversal logic
The fault current reversal logic uses a reverse directed element, connected to input signal IREV,
which recognizes that the fault is in reverse direction. When the reverse direction element is
activated during the
is now ready to handle a current reversal without tripping. Output signal IRVL will be connected to
the block input on the permissive overreaching scheme.
When the fault current is reversed on the non faulty line, IREV is deactivated and IFWD is activated.
The reset of IRVL is delayed by the
received CR signal.
BLOCK
IREV
IFWD
ANSI09000031 V1 EN-US
Figure 193: Simplified logic diagram, current reversal
11.5.6.3 Weak-end infeed logic
The weak-end infeed function can be set to send only an echo signal (
and a trip signal (
The weak-end infeed logic uses normally a reverse and a forward direction element, connected to
WEIBLK1 via an OR-gate. See figure 194. If neither the forward nor the reverse directional
measuring element is activated during the last 200 ms, the weak-end infeed logic echoes back the
received permissive signal. See figure 194.
If the forward or the reverse directional measuring element is activated during the last 200 ms, the
fault current is sufficient for the IED to detect the fault with the ground-fault function that is in
operation.
Line distance protection REL650
Technical manual
and figure 194 show the logic circuits.
tPickUpRev time, the output signal IRVL is activated, see figure 193. The logic
0 0
tPickUp 10ms
Rev
WEI=Echo & Trip ). See figure
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tDelayRev time, see figure 193. This ensures the reset of the
AND
tPickUp
Rev
0
194 and figure 195.
Scheme communication
IRVL
0
tDelay
Rev
Drawing2.vsd
WEI=Echo ) or an echo signal
Section 11
M13929-4 v3
M13929-11 v4
M13929-24 v4
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